EFM8LB1 Datasheet, PDF (11/70 Pages) Silicon Laboratories – The EFM8LB1 device family are fully integrated, mixed-signal system-on-a-chip MCUs. Highlighted features are listed below

3.7 Analog
EFM8LB1 Data Sheet
System Overview
14/12/10-Bit Analog-to-Digital Converter (ADC0)
The ADC is a successive-approximation-register (SAR) ADC with 14-, 12-, and 10-bit modes, integrated track-and hold and a program-
mable window detector. The ADC is fully configurable under software control via several registers. The ADC may be configured to
measure different signals using the analog multiplexer. The voltage reference for the ADC is selectable between internal and external
reference sources.
• Up to 20 external inputs
• Single-ended 14-bit, 12-bit and 10-bit modes
• Supports an output update rate of up to 1 Msps in 12-bit mode
• Channel sequencer logic with direct-to-XDATA output transfers
• Operation in a low power mode at lower conversion speeds
• Asynchronous hardware conversion trigger, selectable between software, external I/O and internal timer and configurable logic sour-
ces
• Output data window comparator allows automatic range checking
• Support for output data accumulation
• Conversion complete and window compare interrupts supported
• Flexible output data formatting
• Includes a fully-internal fast-settling 1.65 V reference and an on-chip precision 2.4 / 1.2 V reference, with support for using the sup-
ply as the reference, an external reference and signal ground
• Integrated factory-calibrated temperature sensor
12-Bit Digital-to-Analog Converters (DAC0, DAC1, DAC2, DAC3)
The DAC modules are 12-bit Digital-to-Analog Converters with the capability to synchronize multiple outputs together. The DACs are
fully configurable under software control. The voltage reference for the DACs is selectable between internal and external reference
sources.
• Voltage output with 12-bit performance
• Hardware conversion trigger, selectable between software, external I/O and internal timer and configurable logic sources
• Outputs may be configured to persist through reset and maintain output state to avoid system disruption
• Multiple DAC outputs can be synchronized together
• DAC pairs (DAC0 and 1 or DAC2 and 3) support complementary output waveform generation
• Outputs may be switched between two levels according to state of configurable logic / PWM input trigger
• Flexible input data formatting
• Supports references from internal supply, on-chip precision reference, or external VREF pin
Low Current Comparators (CMP0, CMP1)
An analog comparator is used to compare the voltage of two analog inputs, with a digital output indicating which input voltage is higher.
External input connections to device I/O pins and internal connections are available through separate multiplexers on the positive and
negative inputs. Hysteresis, response time, and current consumption may be programmed to suit the specific needs of the application.
The comparator includes the following features:
• Up to 10 (CMP0) or 9 (CMP1) external positive inputs
• Up to 10 (CMP0) or 9 (CMP1) external negative inputs
• Additional input options:
• Internal connection to LDO output
• Direct connection to GND
• Direct connection to VDD
• Dedicated 6-bit reference DAC
• Synchronous and asynchronous outputs can be routed to pins via crossbar
• Programmable hysteresis between 0 and ±20 mV
• Programmable response time
• Interrupts generated on rising, falling, or both edges
• PWM output kill feature
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