D2-7XX83 Datasheet, PDF (5/32 Pages) Intersil Corporation – Powered Speaker Systems

D2-7xx83
Absolute Maximum Ratings (Note 7)
Supply Voltage
RVDD, PWMVDD, ADCVDD . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to 4.0V
CVDD, PLLVDD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to 2.4V
Input Voltage
Any Input but XTALI . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to RVDD +0.3V
XTALI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to PLLVDD +0.3V
Input Current, Any Pin but Supplies . . . . . . . . . . . . . . . . . . . . . . . . . . ±10mA
Thermal Information
Thermal Resistance (Typical)
JA (°C/W) JC (°C/W)
128 Ld LQFP Package (Notes 5, 6) . . . . . .
40
6.5
Maximum Storage Temperature. . . . . . . . . . . . . . . . . . . . -55°C to +150°C
Pb-Free Reflow Profile . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . see TB493
Recommended Operating Conditions
Temperature Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -10°C to +85°C
Digital I/O Supply Voltage, PWMVDD . . . . . . . . . . . . . . . . . . . . . . . . . . .3.3V
Core Supply Voltage, CVDD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1.8V
Analog Supply Voltage, PLLVDD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1.8V
CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product
reliability and result in failures not covered by warranty.
NOTES:
5. _JA is measured with the component mounted on a high effective thermal conductivity test board in free air. See Tech Brief TB379 for details.
6. For _JC, the “case temp” location is taken at the package top center.
7. Absolute Maximum parameters are not tested in production.
Electrical Specifications TA = +25°C, CVDD = PLLVDD = 1.8V ±5%, RVDD = PWMVDD = 3.3V ±10%. All grounds at 0.0V. All voltages
referenced to ground. PLL at 294.912MHz, OSC at 24.576MHz, core running at 147.456MHz with typical audio data traffic. Minimum supply currents are
measured in full power down configuration.
SYMBOL
PARAMETER
TEST
MIN
MAX
CONDITIONS
(Note 11)
TYP
(Note 11) UNIT
V_IH Digital Input High Logic Level (Note 8)
RVDD = 3.3V
2.0
-
(Scales with
RVDD)
-
V
V_IL Digital Input Low Logic Level (Note 8)
RVDD = 3.3V
-
-
0.8
V
(Scales with
RVDD)
V_OH High Level Output Drive Voltage
(I_OUT at - Pin Drive Strength Current, see “Pin Descriptions” on
page 11)
RVDD - 0.4
-
-
V
V_OL Low Level Output Drive Voltage
(I_OUT at + Pin Drive Strength Current, see “Pin Descriptions” on
page 11)
-
-
0.4
V
VIHX High Level Input Drive Voltage XTALI Pin
0.7
-
PLLVDD
V
VILX Low Level Input Drive Voltage XTALI Pin
-
-
0.3
V
I_IN
C_IN
VOHO
Input Leakage Current (Note 9)
Input Capacitance
High Level Output Drive Voltage OSCOUT Pin
-
-
-
9
PLLVDD - 0.3
-
±10
µA
-
pF
-
V
VOLO Low Level Output Drive Voltage OSCOUT Pin
-
-
0.3
V
C_OUT Output Capacitance
t_RST nRESET Pulse Width
R_VDD/ Typical Digital and PWM I/O Pad Ring Supply
(Voltage)
PWM_VDD
(Current, Active)
-
9
-
pF
-
10
-
ns
3.0
3.3
3.6
V
-
15
-
mA
(Current, Power-down)
-
<1
-
mA
CVDD Typical Core Supply
(Voltage)
1.7
1.8
1.9
V
(Current, Active)
-
450
-
mA
(Current, Power-down)
-
15
-
mA
PLLVDD Typical PLL Analog Supply
(Voltage)
1.7
1.8
1.9
V
(Current, Active)
-
25
-
mA
(Current, Power-down)
-
10
-
mA
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5
FN7838.3
April 28, 2016