D2-7XX83 Datasheet, PDF (27/32 Pages) Intersil Corporation – Powered Speaker Systems

D2-7xx83
TABLE 6. BOOT MODES
MODE
IRQ[D:A]
M/S
XTALI RANGE
INTERFACE
SPEED
DESCRIPTION
0
0000
S
N/A
per Master I²C port 1 slave boot at address 88
1
0001
M
24.576 MHz
400kb/s
Combo Master - ROM On I²C port 0 or SPI
(See Note 17)
USAGE
System
System
2
0010
M
24.576MHz
1.53MHz
ROM On SPI (EE or FLASH)
(Copy of Mode 1 for pin compatibility)
System
3
0011
S
N/A
per Master SPI slave boot
System
7
0111
S
24.576MHz
384kb/s
Fast Asynchronous SCI boot
Multi-IC
B
1011
S
24.576 MHz
9600 b/s Asynchronous SCI interface boot (RS232
Compatible)
System
C
1100
M
24.576MHz
1.53MHz
HDA enabled, Combo Master - ROM on SPI (EE or
System
(See Note 17) FLASH)
D
1101
M
24.576MHz
400kb/s
Copy of mode C for pin compatibility
System
E
1110
M
24.576MHz
per Master HDA boot
System
F
1111
M
24.576 MHz
400Kb/s
2 wire ROM on GPIO port (SCL= GPIO1,SDA = GPIO0) System/
Failsafe
NOTE:
17. For the “per Master” and “N/A” entries above, there is a maximum transfer rate that is a fraction of XTALI speed. This maximum transfer rate is
peripheral port specific.
APPLICATION FIRMWARE LOAD
The application firmware is loaded either by the boot code or by a
multi-step process. Direct boot code loading occurs when the
selected boot mode successfully finds a boot image on the
expected peripheral interface and the image is successfully
loaded in memory. A multi-step boot is one in which the boot
code loads a program that manages the system boot.
Control Interfaces
I²C 2-WIRE INTERFACE
The D2-7xx83 family IC has two separate I²C 2-Wire compatible
ports. One is typically used for the external microcontroller
interface, and the other for D2-7xx83 family IC communication to
EEPROMs, or other compatible peripheral chips. Both I²C
interfaces are multi-master capable.
Registers are accessed through the I²C control interface. Since
the I²C bus has multiple slaves, the desired I²C target device
must be addressed. The specific I²C channel control address is
defined within the firmware that is loaded into the DAE-6 at boot
and initialization time. Typical addresses used in various
reference designs use the address of 0xB2, but the actual
address should be confirmed based on the firmware design
being used in the application.
SERIAL PERIPHERAL INTERFACE (SPI™)
The Serial Peripheral Interface (SPI) is an alternate serial
interface to the I²C interfaces. As a master, this interface
supports port extenders, EEPROMs, Flash, and various control
interfaces for more complex chips. As a slave, this provides an
alternate method for customers to communicate with the
system.
MULTI-CONTROLLER IC COMMUNICATION
The D2-7xx83 IC is capable of communicating and synchronizing
data and control information across multiple D2-7xx83 ICs. This
communication is to facilitate matrix mixing of all input channels
in a system and to allow precise phase alignment of the output
audio. Systems designs are capable of achieving outputs phase
aligned to within 1/2 sample at 192kHz. One D2-7xx83 IC acts
as the timing master, so all other D2-7xx83 ICs must then
operate as timing slaves. The setting of the each of the D2-7xx83
ICs is system-configuration specific and is detailed in the specific
RDP documentation.
AUDIO SYNCHRONIZATION
Multiple D2-7xx83 ICs can be connected together and synchronized
for controlling events to meet phase alignment requirements.
Control Protocols provide for an external device communication
with the D2-7xx83 firmware while the amplifier is running. The
D2-7xx83 firmware has a peripheral device driver that
establishes communication with the external controller device.
The D2-7xx83 is always a slave. Communication can occur
through the HDA, I²C, and SPI ports. However control is provided
through only the I²C, and HDA ports, and control through the SPI
port is not supported.
CONTROL REGISTER SUMMARY
The control register interface provides a mechanism for an
external controller to manipulate the amplifier signal flow, and
provides access to the internal registers.
Each system design has its own firmware-dependent register
Application Programming Interface (API) and its own unique
signal flow. The control register definitions, bit fields, and data
format for each register are specified in that firmware API.
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FN7838.3
April 28, 2016