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EFM32PG1 Datasheet, PDF (33/94 Pages) Silicon Laboratories – Industrial and factory automation
4.1.15 USART SPI
SPI Master Timing
EFM32PG1 Data Sheet
Electrical Specifications
Table 4.23. SPI Master Timing
Parameter
Symbol
Test Condition
Min
Typ
SCLK period 1 2
tSCLK
2*
-
tHFPERCLK
CS to MOSI 1 2
tCS_MO
0
-
SCLK to MOSI 1 2
tSCLK_MO
3
-
MISO setup time 1 2
tSU_MI
IOVDD = 1.98 V
IOVDD = 3.0 V
56
-
37
-
MISO hold time 1 2
tH_MI
6
-
Note:
1. Applies for both CLKPHA = 0 and CLKPHA = 1 (figure only shows CLKPHA = 0)
2. Measurement done with 8 pF output loading at 10% and 90% of VDD (figure shows 50% of VDD)
Max
Unit
-
ns
8
ns
20
ns
-
ns
-
ns
-
ns
CS
SCLK
CLKPOL = 0
SCLK
CLKPOL = 1
MOSI
MISO
tCS_MO
tSCKL_MO
tSCLK
tSU_MI
tH_MI
Figure 4.1. SPI Master Timing Diagram
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