ISL6742B Datasheet, PDF (3/20 Pages) Intersil Corporation – Fast current sense to output delay

Pin Configuration
ISL6742B
ISL6742B
(16 LD QSOP)
TOP VIEW
VREF 1
VERR 2
RTD 3
CT 4
FB 5
RAMP 6
CS 7
IOUT 8
16 SS
15 VADJ
14 VDD
13 OUTA
12 OUTB
11 OUTAN
10 OUTBN
9 GND
Pin Descriptions
PIN # SYMBOL
DESCRIPTION
1
VREF The 5V reference voltage output having 3% tolerance over line, load and operating temperature. Bypass to GND with a 0.1µF to
2.2µF low ESR capacitor.
2
VERR The VERR pin is the output of the error amplifier and controls the inverting input of the PWM comparator. Feedback compensation
components connect between VERR and FB. There is a nominal 1mA pull-up current source connected to VERR. Soft-start is
implemented as a voltage clamp on the VERR signal.
The outputs, OUTA and OUTB, reduce to 0% duty cycle when VERR is pulled below 0.6V. OUTAN and OUTBN, the complements of
OUTA and OUTB, respectively, go to 100% duty cycle when this occurs.
3
RTD This is the oscillator timing capacitor discharge current control pin. The current flowing in a resistor connected between this pin and
GND determines the magnitude of the current that discharges CT. The CT discharge current is nominally 20x the resistor current.
The PWM dead time is determined by the timing capacitor discharge duration. The voltage at RTD is nominally 2V. The minimum
recommended value of RTD is 2.00kΩ.
4
CT The oscillator timing capacitor is connected between this pin and GND. It is charged through an internal 200µA current source and
discharged with a user adjustable current source controlled by RTD.
5
FB FB is the inverting input to the error amplifier (EA). The amplifier may be used as the error amplifier for voltage feedback or used
as the average current limit amplifier (IEA). If the amplifier is not used, FB should be grounded.
6
RAMP This is the input for the sawtooth waveform for the PWM comparator. The RAMP pin is shorted to GND at the termination of the
PWM signal. A sawtooth voltage waveform is required at this input. For current-mode control this pin is connected directly to CS and
the current loop feedback signal is applied to both inputs. For voltage-mode control, the oscillator sawtooth waveform may be
buffered and used to generate an appropriate signal, or RAMP may be connected to the input voltage through an RC network for
voltage feed forward control, or RAMP may be connected to VREF through an RC network to produce the desired sawtooth
waveform.
7
CS This is the input to the overcurrent comparator and the average current sample and hold circuit. The overcurrent comparator
threshold is set at 1V nominal. The CS pin is shorted to GND at the termination of either PWM output.
Depending on the current sensing source impedance, a series input resistor may be required due to the delay between the internal
clock and the external power switch. This delay may result in CS being discharged prior to the power switching device being turned
off.
8
IOUT Output of the 4x buffer amplifier of the sample and hold circuitry that captures and averages the CS signal.
9
GND Signal and power ground connections for this device. Due to high peak currents and high frequency operation, a low impedance
layout is necessary. Ground planes and short traces are highly recommended.
11, 10 OUTAN and These outputs are the complements of OUTA and OUTB, respectively. These outputs are suitable for control of synchronous
OUTBN rectifiers. The phase relationship between each output and its complement is set by a control voltage applied to VADJ.
13, 12 OUTA and These paired outputs are the pulse width modulated outputs for controlling the switching FETs in alternate sequence.
OUTB
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FN8565.1
November 3, 2015