ISL6742B Datasheet, PDF (10/20 Pages) Intersil Corporation – Fast current sense to output delay

ISL6742B
Electrical Specifications Recommended operating conditions unless otherwise noted. Refer to Figure 1 on page 5, Figure 2 on page 6
and Figure 3 on page 7. 9V < VDD < 16V, RTD = 10.0kΩ, CT = 470pF, T_A = -40°C to +105°C, Typical values are at T_A = +25°C. Boldface limits apply across
the operating temperature range, -40°C to +105°C (Continued)
PARAMETER
TEST CONDITIONS
MIN
MAX
(Note 7)
TYP
(Note 7)
UNIT
High Level Output Voltage (VOH)
Low Level Output Voltage (VOL)
Rise Time
Fall Time
UVLO Output Voltage Clamp (Note 8)
Output Delay/Advance Range
OUTAN/OUTBN Relative to OUTA/OUTB
Delay Control Voltage Range
OUTAN/OUTBN Relative to OUTA/OUTB
I_OUT = -10mA, VDD - VOH
I_OUT = 10mA, VOL - GND
C_OUT = 220pF, VDD = 15V (Note 8)
C_OUT = 220pF, VDD = 15V (Note 8)
VDD = 7V, I_LOAD = 1mA (Note 10)
V_ADJ = 2.50V (Note 8)
V_ADJ < 2.425V
V_ADJ > 2.575V
OUTxN Delayed
OUTx Delayed
-
0.5
1.0
V
-
0.5
1.0
V
-
110
200
ns
-
90
150
ns
-
-
1.25
V
-
-
3
ns
-40
-
-300
ns
40
-
300
ns
2.575
-
5.000
V
0
-
2.425
V
VADJ Delay Time
T_A = +25°C (OUTx Delayed) (Note 11)
VADJ = 0
280
300
320
ns
VADJ = 0.5V
92
105
118
ns
VADJ = 1.0V
61
70
80
ns
VADJ = 1.5V
48
55
65
ns
VADJ = 2.0V
41
50
58
ns
T_A = +25°C (OUTxN Delayed)
VADJ = VREF
280
300
320
ns
VADJ = VREF - 0.5V
86
100
114
ns
VADJ = VREF - 1.0V
59
68
77
ns
VADJ = VREF - 1.5V
47
55
62
ns
VADJ = VREF - 2.0V
41
48
55
ns
THERMAL PROTECTION
Thermal Shutdown
(Note 8)
130
140
150
°C
Thermal Shutdown Clear
(Note 8)
115
125
135
°C
Hysteresis, Internal Protection
(Note 8)
-
15
-
°C
NOTES:
7. Parameters with MIN and/or MAX limits are 100% tested at +25°C, unless otherwise specified. Temperature limits established by characterization
and are not production tested.
8. Limits established by characterization and are not production tested.
9. This is the maximum duty cycle achievable using the specified values of RTD and CT. Larger or smaller maximum duty cycles may be obtained using
other values for these components. See Equations 1 through 3 on page 11.
10. Adjust VDD below the UVLO stop threshold prior to setting at 7V.
11. When OUTx is delayed relative to OUTLxN (VADJ < 2.425V), the delay duration as set by VADJ should not exceed 90% of the CT discharge time (dead
time) as determined by CT and RTD.
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FN8565.1
November 3, 2015