SI4720-B20-GMR Datasheet, PDF (26/48 Pages) Silicon Laboratories – BROADCAST FM RADIO TRANSCEIVER FOR PORTABLE APPLICATIONS

Si4720/21-B20
5.4. Integrated Antenna Support
The Si4720/21 is the first FM receiver to support the fast
growing trend to integrate the FM receiver antenna into
the device enclosure. The chip is designed with this
function in mind from the outset, with multiple
international patents pending, thus it is superior to many
other options in price, board space, and performance.
The Si4720/21 supports an internal RX antenna
allowing for "wire free" listening to FM over Bluetooth.
The user can receive FM over the integrated RX
antenna and stream it via Bluetooth to a Bluetooth-
enabled headset.
Testing indicates that using Silicon Laboratories'
patented techniques provides FM performance over an
integrated antenna that can be very similar in many key
metrics to performance using standard FM receive
antennas (e.g., wired headset). Refer to “AN383:
Antenna Selection and Universal Layout Guidelines” for
additional details on the implementation of support for
an integrated antenna.
Figure 15 shows a conceptual block diagram of the
Si4720/21 architecture used to support the short
antenna. The headphone/dedicated FM receive
antenna is therefore optional. Host software can detect
the presence of a headphone antenna and switch
between the integrated antenna if desired.
Headphone
Ant*
FMI
RFGND
Short/
Embedded
Ant
LPI
L1
120 nH
LNA
AGC
*Note: Dedicated RX antenna is optional.
Figure 15. Conceptual Block Diagram of the
Si4720/21 Short Antenna Support
5.5. Receiver Digital Audio Interface
(Si4721 Only)
The digital audio interface operates in slave mode and
supports three different audio data formats:
 I²S
 Left-Justified
 DSP Mode
5.5.1. Audio Data Formats
In I²S mode, by default the MSB is captured on the
second rising edge of DCLK following each DFS
transition. The remaining bits of the word are sent in
order, down to the LSB. The left channel is transferred
first when the DFS is low, and the right channel is
transferred when the DFS is high.
In Left-Justified mode, by default the MSB is captured
on the first rising edge of DCLK following each DFS
transition. The remaining bits of the word are sent in
order, down to the LSB. The left channel is transferred
first when the DFS is high, and the right channel is
transferred when the DFS is low.
In DSP mode, the DFS becomes a pulse with a width of
1DCLK period. The left channel is transferred first,
followed right away by the right channel. There are two
options in transferring the digital audio data in DSP
mode: the MSB of the left channel can be transferred on
the first rising edge of DCLK following the DFS pulse or
on the second rising edge.
In all audio formats, depending on the word size, DCLK
frequency, and sample rates, there may be unused
DCLK cycles after the LSB of each word before the next
DFS transition and MSB of the next word. In addition, if
preferred, the user can configure the MSB to be
captured on the falling edge of DCLK via properties.
The number of audio bits can be configured for 8, 16,
20, or 24 bits.
5.5.2. Audio Sample Rates
The device supports a number of industry-standard
sampling rates including 32, 40, 44.1, and 48 kHz. The
digital audio interface enables low-power operation by
eliminating the need for redundant DACs on the audio
baseband processor.
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Rev. 1.0