SI4438 Datasheet, PDF (24/44 Pages) Silicon Laboratories – Low active power consumption

Si4438
The RSSI values and curves may be offset by the MODEM_RSSI_COMP property. The default value of 7’h32
corresponds to no RSSI offset. Setting a value less than 7’h32 corresponds to a negative offset, and a value higher
than 7’h32 corresponds to a positive offset. The offset value is in 1 dB steps. For example, setting a value of 7’h3A
corresponds to a positive offset of 8 dB.
Clear channel assessment (CCA) or RSSI threshold detection is also available. An RSSI threshold may be set in
the MODEM_RSSI_THRESH API property. If the RSSI value is above this threshold, an interrupt or GPIO may
notify the host. Both the latched version and asynchronous version of this threshold are available on any of the
GPIOs. Automatic fast hopping based on RSSI is available. See “5.3.1.2. Automatic RX Hopping and Hop Table”.
5.3. Synthesizer
An integrated Sigma Delta () Fractional-N PLL synthesizer capable of operating over 425–525 MHz. Using a 
synthesizer has many advantages; it provides flexibility in choosing data rate, deviation, channel frequency, and
channel spacing. The transmit modulation is applied directly to the loop in the digital domain through the fractional
divider, which results in very precise accuracy and control over the transmit deviation. The frequency resolution in
the 425–525 MHz band is 14.3 Hz with more resolution in the other bands. The nominal reference frequency to the
PLL is 30 MHz, but any XTAL frequency from 25 to 32 MHz may be used. The modem configuration calculator in
WDS will automatically account for the XTAL frequency being used. The PLL utilizes a differential LC VCO with
integrated on-chip inductors. The output of the VCO is followed by a configurable divider, which will divide the
signal down to the desired output frequency band.
5.3.1. Synthesizer Frequency Control
The frequency is set by changing the integer and fractional settings to the synthesizer. The WDS calculator will
automatically provide these settings, but the synthesizer equation is shown below for convenience. The APIs for
setting the frequency are FREQ_CONTROL_INTE, FREQ_CONTROL_FRAC2, FREQ_CONTROL_FRAC1, and
FREQ_CONTROL_FRAC0.
RF_channel
=


fc_inte
+
-^f-^c---_{2_}----^f₁-^r-₉-^a---^c--_
 ²-----^-_o----_uf--^r--_te--_d-^q---_i-^_v---^x---^o--Hz
Note: The fc_frac/2¹⁹ value in the above formula has to be a number between 1 and 2.
5.3.1.1. EZ Frequency Programming
In applications that utilize multiple frequencies or channels, it may not be desirable to write four API registers each
time a frequency change is required. EZ frequency programming is provided so that only a single register write
(channel number) is required to change frequency. A base frequency is first set by first programming the integer
and fractional components of the synthesizer. This base frequency will correspond to channel 0. Next, a channel
step size is programmed into the FREQ_CONTROL_CHANNEL_STEP_SIZE_1 and
FREQ_CONTROL_CHANNEL_STEP_SIZE_0 API registers. The resulting frequency will be:
RF Frequency = Base Frerquency + Channel  Stepsize
The second argument of the START_RX or START_TX is CHANNEL, which sets the channel number for EZ
frequency programming. For example, if the channel step size is set to 1 MHz, the base frequency is set to
490 MHz with the INTE and FRAC API registers, and a CHANNEL number of 5 is programmed during the
START_TX command, the resulting frequency will be 495 MHz. If no CHANNEL argument is written as part of the
START_RX/TX command, it will default to the previous value. The initial value of CHANNEL is 0; so, if no
CHANNEL value is written, it will result in the programmed base frequency.
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