SI4438 Datasheet, PDF (23/44 Pages) Silicon Laboratories – Low active power consumption

Si4438
5.2.1. Automatic Gain Control (AGC)
The AGC algorithm is implemented digitally using an advanced control loop optimized for fast response time. The
AGC occurs within a single bit or in less than 2 µs. Peak detectors at the output of the LNA and PGA allow for
optimal adjustment of the LNA gain and PGA gain to optimize IM3, selectivity, and sensitivity performance.
5.2.2. Auto Frequency Correction (AFC)
Frequency mistuning caused by crystal inaccuracies can be compensated for by enabling the digital automatic
frequency control (AFC) in receive mode. There are two types of integrated frequency compensation: modem
frequency compensation, and AFC by adjusting the PLL frequency. With AFC disabled, the modem compensation
can correct for frequency offsets up to ±0.25 times the IF bandwidth. When the AFC is enabled, the received signal
will be centered in the pass-band of the IF filter, providing optimal sensitivity and selectivity over a wider range of
frequency offsets up to ±0.35 times the IF bandwidth. When AFC is enabled, the preamble length needs to be long
enough to settle the AFC. As shown in Table 13 on page 21, an additional byte of preamble is typically required to
settle the AFC.
5.2.3. Received Signal Strength Indicator
The received signal strength indicator (RSSI) is an estimate of the signal strength in the channel to which the
receiver is tuned. The RSSI measurement is done after the channel filter, so it is only a measurement of the
desired or undesired in-band signal power. There are two different methods for reading the RSSI value and several
different options for configuring the RSSI value that is returned. The fastest method for reading the RSSI is to
configure one of the four fast response registers (FRR) to return a latched RSSI value. The latched RSSI value is
measured once per packet and is latched at a configurable amount of time after RX mode is entered. The fast
response registers can be read in 16 SPI clock cycles with no requirement to wait for CTS. The RSSI value may
also be read out of the GET_MODEM_STATUS command. In this command, both the current RSSI and the latched
RSSI are available. The current RSSI value represents the signal strength at the instant in time the
GET_MODEM_STATUS command is processed and may be read multiple times per packet. Reading the RSSI in
the GET_MODEM_STATUS command takes longer than reading the RSSI out of the fast response register. After
the initial command, it will take 33 μs for CTS to be set and then the four or five bytes of SPI clock cycles to read
out the respective current or latched RSSI values.
The RSSI configuration options are set in the MODEM_RSSI_CONTROL API property. The latched RSSI value
may be latched and stored based on the following events: preamble detection, sync detection, or a configurable
number of bit times measured after the start of RX mode (minimum of 4 bit times). The requirement for four bit
times is determined by the processing delay and settling through the modem and digital channel filter. In
MODEM_RSSI_CONTROL, the RSSI may be defined to update every bit period or to be averaged and updated
every four bit periods. If RSSI averaging over four bits is enabled, the latched RSSI value will be delayed to a
minimum of 7 bits after the start of RX mode to allow for the averaging. The latched RSSI values are cleared when
entering RX mode so they may be read after the packet is received or after dropping back to standby mode. If the
RSSI value has been cleared by the start of RX but not latched yet, a value of 0 will be returned if it is attempted to
be read.
The RSSI value read by the API could be translated to dBm by the following linear equation:
RSSI_dBm = ^R-----^S-----^S----^I-₂-^_---^v---^a----^l-^u---^e-- – 130
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