ISL12024IRTC Datasheet, PDF (2/24 Pages) Intersil Corporation – Real-Time Clock/Calendar

ISL12024IRTC
Block Diagram
OSC
COMPENSATION
X1
32.768kHz
X2
IRQ/F_OUT
SELECT
OSCILLATOR
FREQUENCY
DIVIDER
1Hz
TIMER
CALENDAR
LOGIC
TIME
KEEPING
REGISTERS
(SRAM)
SCL
SDA
SERIAL
INTERFACE
DECODER
CONTROL
DECODE
LOGIC
CONTROL/
REGISTERS
(EEPROM)
8
STATUS
REGISTERS
(SRAM)
ALARM
COMPARE
ALARM REGS
(EEPROM)
4k
EEPROM
ARRAY
BATTERY
SWITCH
CIRCUITRY
VDD
VBAT
Pin Descriptions
PIN
NUMBER
TDFN
1
2
3
4
5
6
7
8
SYMBOL
X1
X2
IRQ/F_OUT
GND
SDA
SCL
VBAT
VDD
DESCRIPTION
The X1 pin is the input of an inverting amplifier and is intended to be connected to one pin of an external 32.768kHz
quartz crystal.
The X2 pin is the output of an inverting amplifier and is intended to be connected to one pin of an external 32.768kHz
quartz crystal. (See “Application Section” on page 20.)
Interrupt Output/Frequency Output is a multi-functional pin that can be used as interrupt or frequency output pin. The
function is set via the control register. This output is an open drain configuration.
Ground.
Serial Data (SDA) is a bidirectional pin used to transfer serial data into and out of the device. It has an open drain
output and may be wire OR’ed with other open drain or open collector outputs.
The Serial Clock (SCL) input is used to clock all serial data into and out of the device. The input buffer on this pin is
always active (not gated).
This input provides a backup supply voltage to the device. V_BAT supplies power to the device in the event that the
V_DD supply fails. This pin should be tied to ground if not used.
Power Supply.
2
FN6749.1
December 15, 2011