ISL12024IRTC Datasheet, PDF (17/24 Pages) Intersil Corporation – Real-Time Clock/Calendar

ISL12024IRTC
Write Operations
Byte Write
For a write operation, the device requires the Slave Address
Byte and the Word Address Bytes. This gives the master
access to any one of the words in the array or CCR.
(Note: Prior to writing to the CCR, the master must write a
02h, then 06h to the status register in two preceding
operations to enable the write operation. See “Writing to the
Clock/Control Registers” on page 12). Upon receipt of each
address byte, the ISL12024IRTCZ responds with an
acknowledge. After receiving both address bytes the
ISL12024IRTCZ awaits the 8 bits of data. After receiving the
8 data bits, the ISL12024IRTCZ again responds with an
acknowledge. The master then terminates the transfer by
generating a stop condition. The ISL12024IRTCZ then
begins an internal write cycle of the data to the nonvolatile
memory. During the internal write cycle, the device inputs
are disabled, so the device will not respond to any requests
from the master. The SDA output is at high impedance. (See
Figure 16).
A write to a protected block of memory is ignored, but will still
receive an acknowledge. At the end of the write command,
the ISL12024IRTCZ will not initiate an internal write cycle,
and will continue to ACK commands.
Byte writes to all of the non-volatile registers are allowed,
except the DWAn registers which require multiple byte writes
or page writes to trigger non-volatile writes. See “Device
Operation” on page 12 for more information.
Page Write
The ISL12024IRTCZ has a page write operation. It is
initiated in the same manner as the byte write operation; but
instead of terminating the write cycle after the first data byte
is transferred, the master can transmit up to 15 more bytes
to the memory array and up to 7 more bytes to the
clock/control registers. The RTC registers require a page
write (8 bytes), individual register writes are not allowed.
(Note: Prior to writing to the CCR, the master must write a
02h, then 06h to the status register in two preceding
operations to enable the write operation. See “Writing to the
Clock/Control Registers” on page 12.)
After the receipt of each byte, the ISL12024IRTCZ responds
with an acknowledge, and the address is internally
incremented by one. The address pointer remains at the last
address byte written. When the counter reaches the end of
the page, it “rolls over” and goes back to the first address on
the same page. This means that the master can write 16
bytes to a memory array page or 8 bytes to a CCR section
starting at any location on that page. For example, if the
master begins writing at location 10 of the memory and loads
15 bytes, then the first 6 bytes are written to addresses 10
through 15, and the last 6 bytes are written to columns 0
through 5. Afterwards, the address counter would point to
location 6 on the page that was just written. If the master
supplies more than the maximum bytes in a page, then the
previously loaded data is over-written by the new data, one
byte at a time (see Figure 17). The master terminates the
Data Byte loading by issuing a stop condition, which causes
the ISL12024IRTCZ to begin the non-volatile write cycle. As
with the byte write operation, all inputs are disabled until
completion of the internal write cycle. See Figure 18 for the
address, acknowledge and data transfer sequence.
Stops and Write Modes
Stop conditions that terminate write operations must be sent
by the master after sending at least 1 full data byte and its
associated ACK signal. If a stop is issued in the middle of a
data byte, or before 1 full data byte + ACK is sent, then the
ISL12024IRTCZ resets itself without performing the write.
The contents of the array are not affected.
SIGNALS FROM
THE MASTER
SDA BUS
SIGNALS FROM
THE SLAVE
S
T
A
R SLAVE
T ADDRESS
WORD
ADDRESS 1
WORD
ADDRESS 0
S
T
O
DATA
P
1
1 110 0000000
A
A
A
A
C
C
C
C
K
K
K
K
FIGURE 16. BYTE WRITE SEQUENCE
17
FN6749.1
December 15, 2011