ISL12024IRTC Datasheet, PDF (16/24 Pages) Intersil Corporation – Real-Time Clock/Calendar

ISL12024IRTC
Device Addressing
Following a start condition, the master must output a Slave
Address Byte. The first four bits of the Slave Address Byte
specify access to either the EEPROM array or to the CCR.
Slave bits ‘1010’ access the EEPROM array. Slave bits
‘1101’ access the CCR.
When shipped from the factory, EEPROM array is
UNDEFINED, and should be programmed by the customer
to a known state.
Bit 3 through Bit 1 of the slave byte specify the device select
bits. These are set to ‘111’.
The last bit of the Slave Address Byte defines the operation
to be performed. When this R/W bit is a one, then a read
operation is selected. A zero selects a write operation (see
Figure 15.)
After loading the entire Slave Address Byte from the SDA bus,
the ISL12024IRTCZ compares the device identifier and device
select bits with ‘1010111’ or ‘1101111’. Upon a correct compare,
the device outputs an acknowledge on the SDA line.
Following the Slave Byte is a two byte word address. The
word address is either supplied by the master device or
obtained from an internal counter. On power-up, the internal
address counter is set to address 0h, so a current address
read of the EEPROM array starts at address 0. When
required, as part of a random read, the master must supply
the 2 Word Address Bytes as shown in Figure 15.
In a random read operation, the slave byte in the “dummy
write” portion must match the slave byte in the “read”
section. That is if the random read is from the array the slave
byte must be 1010111x in both instances. Similarly, for a
random read of the Clock/Control Registers, the slave byte
must be 1101111x in both places.
DEVICE IDENTIFIER
ARRAY
CCR
1
0
1
0
1
1
0
1
1
1
1
R/W
0
0
0
0
0
0
0
A8
A7
A6
A5
A4
A3
A2
A1
A0
SLAVE ADDRESS BYTE
BYTE 0
WORD ADDRESS 1
BYTE 1
WORD ADDRESS 0
BYTE 2
D7
D6
D5
D4
D3
D2
D1
D0
DATA BYTE
BYTE 3
FIGURE 15. SLAVE ADDRESS, WORD ADDRESS, AND DATA BYTES (16 BYTE PAGES)
16
FN6749.1
December 15, 2011