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C8051T620-DK Datasheet, PDF (2/30 Pages) Silicon Laboratories – C8051T620/2 DEVELOPMENT KIT USER’S GUIDE
C8051T620/2-DK
3. Hardware Setup
See Figure 1 for a diagram of the hardware configuration.
1. Attach the desired daughter board to the motherboard at connectors P1 and P2.
2. If using the QFN Socket Daughter Board, place the device to be programmed into the socket.
3. Place shorting blocks on J7 and the +3VD-VDD_PWR jumper pair on J6, as shown in Figure 1.
4. Connect the motherboard’s P5 USB connector to a PC running the Silicon Laboratories IDE using the USB
Cable.
5. Connect the ac-to-dc power adapter to connector P3 on the motherboard.
Notes:
1. Use the Reset icon in the IDE to reset the target when connected during a debug session.
2. Remove power from the motherboard and remove the USB cable before removing a daughter board from the
motherboard. Connecting or disconnecting a daughter board when the power adapter or USB cable are connected can
damage the motherboard, the daughter board, or the socketed device.
3. Remove power from the motherboard and remove the USB cable before removing a C8051T62x/32x device from the
socket. Inserting or removing a device from the socket when the power adapter or USB cable are connected can
damage the motherboard, the daughter board, or the socketed device.
4. The above hardware setup instructions configure the development system to be powered through the onboard 3.3 V
regulator. For other power options, see "7.3. Power Supply Headers (J6 and J7)" on page 15.
C8051T62x EDB J1
J1C8051T62x-MB
P3
U1
P1
F34A
SILICON LABS
www.silabs.com
VBUS
VDD
VREGIN
VREGIN
LED1
SW1 LED2
SW2
J14
P1.0
SW2
P2.1
P0.1 P1.2
SW1 LED2
P2.0 P2.3
P0.6
LED1
P2.2
J9
J10
J2
J15
SILICON LABS
www.silabs.com
P3
VPP
J3
J7
PWR
J6
+3VD
VDD_PWR
VDD_EXT
VDD_PWR
J4
VDD_DEBUG
VDD_COMM
VDD_PWR
VDD_PWR
USPB2ACTIVE
J5
U2 USB ACTIVE
CP2103
P4
J8
RTS_DEBUG
CTS_DEBUG
P1.1
P1.2
RTS_COMM
CTS_COMM
J11
RX_DEBUG
TX_DEBUG
P0.4
P0.5
RX_COMM
TX_COMM
D10 D11 D12
RUN
STOP DEBUG
PWR
U1
F326
J12 J13
P5
R8
RESET
AC Adapter
Place shorting blocks on
J7 and J6 as shown.
USB Cable
Figure 1. Hardware Setup (Emulation Daughter Board)
2
Rev. 0.5