C8051T620-DK Datasheet, PDF (17/30 Pages) Silicon Laboratories – C8051T620/2 DEVELOPMENT KIT USER’S GUIDE

C8051T620/2-DK
7.8. Analog I/O (J1 and J14)
Three of the C8051T62x/32x target device's port pins are connected to the J1 terminal block. The terminal block
also allows users to input an external voltage that can be used as the power supply of the board. Refer to Table 3
for the J1 terminal block connections. Placing a shorting block on J14 will connect the P0.7/VREF signal on J1 to
the P0.7 pin of the device.
Table 3. J1 Terminal Block Descriptions
Pin #
1
2
3
4
5
6
Description
VREGIN
VIO
GND
P2.5 (Analog Input)
P0.7/VREF (routed to header J14)
VDD_EXT (routed to header J6)
7.9. VPP Connection (J15)
The C8051T62x/32x devices require an external 6.0 V programming voltage applied to the VPP pin during device
programming. The VPP pin on these devices is shared with P1.5 or P1.1 depending on the device. During
programming, the VPP voltage is automatically enabled when needed. Header J15 is provided to allow the user to
disconnect the programming circuitry from the VPP pin to avoid interfering with the normal application operation of
the GPIO pin. When programming the device, J15 should be shorted with a shorting block. When running normal
application code, J15 can be removed. See Table 4 for more information on which port pins are shared with VPP.
Table 4. VPP Pin Sharing
Device
C8051T620
C8051T621
C8051T626
C8051T627
C8051T320
C8051T321
C8051T322
C8051T323
C8051T622
C8051T623
C8051T326
C8051T327
Pin Shared with VPP
P1.5
P1.1
Rev. 0.5
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