SI53159-A01AGM Datasheet, PDF (19/22 Pages) Silicon Laboratories – PCI-EXPRESS GEN 1, GEN 2, & GEN 3 NINE OUTPUT FANOUT BUFFER

Si53159
7. Package Outline
Figure 4 illustrates the package details for the Si53159. Table 7 lists the values for the dimensions shown in the
illustration.
Figure 4. 48-Pin Quad Flat No Lead (QFN) Package
Table 7. Package Diagram Dimensions
Symbol
Millimeters
Min
Nom
Max
A
0.70
0.75
0.80
A1
0.00
0.025
0.05
b
0.15
0.20
0.25
D
6.00 BSC
D2
4.30
4.40
4.50
e
0.40 BSC
E
6.00 BSC
E2
4.30
4.40
4.50
L
0.30
0.40
0.50
aaa
0.10
bbb
0.10
ccc
0.08
ddd
0.07
Notes:
1. All dimensions shown are in millimeters (mm) unless otherwise
noted.
2. Dimensioning and Tolerancing per ANSI Y14.5M-1994.
3. This drawing conforms to JEDEC outline MO-220, variation VGGD-8
4. Recommended card reflow profile is per the JEDEC/IPC J-STD-020
specification for Small Body Components
Rev. 1.0
19