SI53159-A01AGM Datasheet, PDF (16/22 Pages) Silicon Laboratories – PCI-EXPRESS GEN 1, GEN 2, & GEN 3 NINE OUTPUT FANOUT BUFFER

Si53159
Pin #
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
Name
OE_DIFF3
OE_DIFF[4:5]
OE_DIFF[6:8]
VDD_DIFF
VDD_DIFF
DIFF0
DIFF0
VSS_DIFF
DIFF1
DIFF1
DIFF2
DIFF2
DIFF3
DIFF3
VDD_DIFF
VSS_DIFF
DIFF4
DIFF4
DIFF5
DIFF5
VSS_DIFF
DIFF6
DIFF6
DIFF7
DIFF7
VDD_DIFF
DIFF8
DIFF8
SCLK
Table 6. Si53159 48-Pin QFN Descriptions
Type
Description
I,PU Active high input pin enables DIFF3 (internal 100 k pull-up).
I,PU Active high input pin enables DIFF[4:5] (internal 100 k pull-up).
I,PU Active high input pin enables DIFF[6:8] (internal 100 k pull-up).
PWR 3.3 V power supply.
PWR 3.3 V power supply.
O, DIF 0.7 V, 100 MHz differential clock.
O, DIF 0.7 V, 100 MHz differential clock.
GND Ground.
O, DIF 0.7 V, 100 MHz differential clock.
O, DIF 0.7 V, 100 MHz differential clock.
O, DIF 0.7 V, 100 MHz differential clock.
O, DIF 0.7 V, 100 MHz differential clock.
O, DIF 0.7 V, 100 MHz differential clock.
O, DIF 0.7 V, 100 MHz differential clock.
PWR 3.3V power supply.
GND Ground.
O, DIF 0.7 V, 100 MHz differential clock.
O, DIF 0.7 V, 100 MHz differential clock.
O, DIF 0.7 V, 100 MHz differential clock.
O, DIF 0.7 V, 100 MHz differential clock.
GND Ground.
O, DIF 0.7 V, 100 MHz differential clock.
O, DIF 0.7 V, 100 MHz differential clock.
O, DIF 0.7 V, 100 MHz differential clock.
O, DIF 0.7 V, 100 MHz differential clock.
PWR 3.3 V power supply.
O, DIF 0.7 V, 100 MHz differential clock.
O, DIF 0.7 V, 100 MHz differential clock.
I I²C compatible SCLOCK.
16
Rev. 1.0