SI53159-A01AGM Datasheet, PDF (1/22 Pages) Silicon Laboratories – PCI-EXPRESS GEN 1, GEN 2, & GEN 3 NINE OUTPUT FANOUT BUFFER

Si53159
PCI-EXPRESS GEN 1, GEN 2, & GEN 3 NINE OUTPUT
FANOUT BUFFER
Features
 PCI-Express Gen 1, Gen 2, and  100 to 210 MHz clock input range
Gen 3 compliant
 I²C support with readback
 Supports Serial-ATA (SATA) at
capabilities
100 MHz
 Supports spread spectrum input
 Low power push-pull differential _{ Extended temperature:}
output buffers
 No termination resistors required
–40 to 85 ^oC
 Output enable pins for all
 3.3 V power supply
buffered clocks
 48-pin QFN package
 Up to nine buffered clocks
Applications
Ordering Information:
See page 18.
 Network attached storage
 Multi-function printers
 Wireless access point
 Servers
Pin Assignments
Description
The Si53159 is a high-performance, low additive, PCIe clock buffer that
can fan out nine PCIe clocks. The clock outputs are compliant to PCIe
Gen 1, Gen 2, and Gen 3 specifications. The device has six hardware
output enable control pins for enabling and disabling differential outputs.
The small footprint and low power consumption makes the Si53159 the
ideal clock solution for consumer and embedded applications.
Functional Block Diagram
48 47 46 45 44 43 42 41 40 39 38 37
VDD_DIFF 1
36 DIFF8
VDD_DIFF 2
35 DIFF8
OE_DIFF0¹ 3
34 VDD_DIFF
OE_DIFF1¹ 4
VDD_DIFF 5
VSS_DIFF 6
VSS_DIFF 7
OE_DIFF2¹ 8
OE_DIFF3¹ 9
OE_DIFF[4:5]¹ 10
OE_DIFF[6:8]¹ 11
VDD_DIFF 12
49
GND
33 DIFF7
32 DIFF7
31 DIFF6
30 DIFF6
29 VSS_DIFF
28 DIFF5
27 DIFF5
26 DIFF4
25 DIFF4
13 14 15 16 17 18 19 20 21 22 23 24
DIFFIN
DIFFIN
SCLK
SDATA
OE [8:0]
Control & Memory
Control RAM
DIFF0
DIFF1
DIFF2
DIFF3
DIFF4
DIFF5
DIFF6
DIFF7
DIFF8
Notes:
1. Internal 100 kohm pull-up.
2. Internal 100 kohm pull-down.
Patents pending
Rev. 1.0 5/12
Copyright © 2012 by Silicon Laboratories
Si53159