SI4708-C Datasheet, PDF (18/40 Pages) Silicon Laboratories – BROADCAST FM RADIO TUNER FOR PORTABLE APPLICATIONS

Si4708/09-C
4.10. Audio Output Summation
The audio outputs LOUT and ROUT may be
capacitively summed with another device. Setting the
audio high-Z enable (AHIZEN) bit maintains a dc bias of
0.5 x V_IO on the LOUT and ROUT pins to prevent the
ESD diodes from clamping to the V_IO or GND rail in
response to the output swing of the other device. The
bias point is set with a 370 k resistor to V_IO and GND.
Register 07h containing the AHIZEN bit must not be
written during the powerup sequence and only takes
effect when in powerdown and V_IO is supplied. In
powerup the LOUT and ROUT pins are set to the
common mode voltage specified in Table 7, “FM
Receiver Characteristics^1,2,” on page 10, regardless of
the state of AHIZEN. Bits 13:0 of register 07h must be
preserved as 0x0100 while in powerdown and as
0x3C04 while in powerup.
4.11. Initialization Sequence
1. Note that V_IO is still supplied in this scenario. If V_IO is
not supplied, refer to device initialization procedure
above.
2. (Optional) Set the AHIZEN bit low to disable the dc
bias of 0.5 x V_IO volts at the LOUT and ROUT pins,
but preserve the states of the other bits in Register
07h. Note that in powerup the LOUT and ROUT pins
are set to the common mode voltage specified in
Table 7 on page 10, regardless of the state of
AHIZEN.
3. Supply V_A and V_D.
4. Provide RCLK. Steps 3 and 4 may be reversed when
using an external oscillator.
5. Set the ENABLE bit high and the DISABLE bit low to
powerup the device. Software should wait for the
powerup time (as specified by Table 7, “FM Receiver
Characteristics^1,2,” on page 10) before continuing
with normal part operation.
Refer to Figure 8, “Initialization Sequence,” on page 18.
To initialize the device:
1. Supply V_A and V_D.
2. Supply V_IO while keeping the RST pin low. Note that
steps 1 and 2 may be reversed. Power supplies may
be sequenced in any order.
3. Select 2-wire or 3-wire control interface bus mode
operation as described in Section 4.9. "Reset,
Powerup, and Powerdown" on page 17.
4. Provide RCLK. Steps 3 and 4 may be reversed when
using an external oscillator.
5. Set the ENABLE bit high and the DISABLE bit low to
powerup the device. Software should wait for the
powerup time (as specified by Table 7, “FM Receiver
Characteristics^1,2,” on page 10) before continuing
with normal part operation.
To power down the device:
1. (Optional) Set the AHIZEN bit high to maintain a dc
bias of 0.5 x V_IO volts at the LOUT and ROUT pins
while in powerdown, but preserve the states of the
other bits in Register 07h. Note that in powerup the
LOUT and ROUT pins are set to the common mode
voltage specified in Table 7 on page 10, regardless
of the state of AHIZEN.
2. Set the ENABLE bit high and the DISABLE bit high
to place the device in powerdown mode. Note that all
register states are maintained so long as V_IO is
supplied and the RST pin is high.
3. (Optional) Remove RCLK.
4. Remove V_A and V_D supplies as needed.
To power up the device (after power down):
VA,VD Supply
VIO Supply
RST Pin
RCLK Pin
ENABLE Bit
1
2
3
4
5
Figure 8. Initialization Sequence
4.12. Programming Guide
Refer to "AN349: Si4708/09 Programming Guide" for
control interface programming information.
18
Rev. 1.2