SI4708-C Datasheet, PDF (16/40 Pages) Silicon Laboratories – BROADCAST FM RADIO TUNER FOR PORTABLE APPLICATIONS

Si4708/09-C
was unable to find a channel, the seek failure/band limit
(SF/BL) bit will be set high and the device will return to
the channel selected before the seek operation began.
When the SKMODE bit is high and a seek is initiated,
the device seeks through the band until the band limit is
reached and the SF/BL bit will be set high. A seek
operation is initiated by setting the SEEK and SEEKUP
bits. After the seek operation completes, the STC bit will
be set, and the RSSI level and tuned channel are
available by reading bits RSSI[7:0] and bits
READCHAN[9:0]. During a seek operation
READCHAN[9:0] is also updated and may be read to
determine seek progress. The STC bit will be set after
the seek operation completes. The channel is valid if the
seek operation completes and the SF/BL bit is set low.
At other times, such as before a seek operation or after
a seek completes and the SF/BL bit is set high, the
channel is valid if the AFC Rail (AFCRL) bit is set low
and the value of RSSI[7:0] is greater than or equal to
SEEKTH[7:0]. Note that if the AFCRL bit is set, the
audio output is muted as in the softmute case discussed
in Section “4.5. Stereo Audio Processing”. The SEEK bit
must be set low after the STC bit is set high in order to
complete the seek operation and clear the STC and
SF/BL bits. The seek operation may be aborted by
setting the SEEK bit low at any time.
The device can be configured to generate an interrupt
on GPO when a tune or seek operation completes.
Setting the seek/tune complete (STCIEN) bit and
GPO[1:0] = 01 will configure GPO for a 5 ms low
interrupt when the STC bit is set by the device.
For additional recommendations on optimizing the seek
function, consult "AN349: Si4708/09 Programming
Guide."
4.7. Reference Clock
4.8. Control Interface
Two-wire slave-transceiver and three-wire interfaces
are provided for the controller IC to read and write the
control registers. Refer to “4.9. Reset, Powerup, and
Powerdown” for a description of bus mode selection.
Registers may be written and read when the V_IO supply
is applied regardless of the state of the V_D or V_A
supplies. RCLK is not required for proper register
operation.
4.8.1. 3-Wire Control Interface
For three-wire operation, a transfer begins when the
SEN pin is sampled low by the device on a rising SCLK
edge. The control word is latched internally on rising
SCLK edges and is nine bits in length, comprised of a
four bit chip address A7:A4 = 0110b, a read/write bit
(write = 0 and read = 1), and a four bit register address,
A3:A0. The ordering of the control word is A7:A5, R/W,
A4:A0. Refer to Section 5. "Register Summary" on page
19 for a list of all registers and their addresses.
For write operations, the serial control word is followed
by a 16-bit data word and is latched internally on rising
SCLK edges.
For read operations, a bus turn-around of half a cycle is
followed by a 16-bit data word shifted out on rising
SCLK edges and is clocked into the system controller
on falling SCLK edges. The transfer ends on the rising
SCLK edge after SEN is set high. Note that 26 SCLK
cycles are required for a transfer, however, SCLK may
run continuously.
For details on timing specifications and diagrams, refer
to Table 5, “3-Wire Control Interface Characteristics,” on
page 7, Figure 2, “3-Wire Control Interface Write Timing
Parameters,” on page 7, and Figure 3, “3-Wire Control
Interface Read Timing Parameters,” on page 7.
The Si4708/09-C accepts a 32.768 kHz reference clock
to the RCLK pin. The reference clock is required
whenever the ENABLE bit is set high. Refer to Table 3,
“DC Characteristics,” on page 5 for input switching
voltage levels and Table 7, "FM Receiver
Characteristics," on page 10 for frequency tolerance
information.
16
Rev. 1.2