SI4708-C Datasheet, PDF (14/40 Pages) Silicon Laboratories – BROADCAST FM RADIO TUNER FOR PORTABLE APPLICATIONS

Si4708/09-C
4.2. FM Receiver
The Si4708/09 architecture and antenna design
increases system performance. To ensure proper
performance and operation, designers should refer to
the guidelines in "AN350: Si4708/09 Antenna,
Schematic, Layout, and Design Guidelines".
Conformance to these guidelines will help to ensure
excellent performance in weak signal, noisy, and
crowded signal environments where many strong
channels are present.
The Si4708/09’s patented digital low-IF architecture
reduces external components and eliminates the need
for factory adjustments. The receive (RX) section
integrates a low noise amplifier (LNA) supporting the
worldwide FM broadcast band (76 to 108 MHz). An
automatic gain control (AGC) circuit controls the gain of
the LNA to optimize sensitivity and rejection of strong
interferers.
An image-reject mixer downconverts the RF signal to
low-IF. The quadrature mixer output is amplified,
filtered, and digitized with high resolution
analog-to-digital converters (ADCs). This advanced
architecture achieves superior performance by using
digital signal processing (DSP) to perform channel
selection, FM demodulation, and stereo audio
processing compared to traditional analog
architectures.
4.3. General Purpose Output
The GPO pin can serve multiple functions. After
powerup of the device, the GPO pin can be used as a
general purpose input/output, and can be used as an
interrupt request pin for the seek/tune or RDS ready
functions. See register 04h, bits [3:2] in Section “6.
Register Descriptions” for information on GPO control. It
is recommended that the GPO pin not be used as an
interrupt request output until the powerup time has
completed (see Section “4.9. Reset, Powerup, and
Powerdown”). The GPO pin is powered from the V_IO
supply; therefore, general purpose input/output
functionality is available regardless of the state of the V_A
and V_D supplies, or the ENABLE and DISABLE bits.
4.4. RDS/RBDS Processor and
Functionality
The Si4709 implements an RDS/RBDS processor for
symbol decoding, block synchronization, error
detection, and error correction. RDS functionality is
enabled by setting the RDS bit. The device offers two
RDS modes, a standard mode and a verbose mode.
The primary difference is increased visibility to RDS
block-error levels and synchronization status with
verbose mode.
Setting the RDS mode (RDSM) bit low places the
device in standard RDS mode (default). The device will
set the RDS ready (RDSR) bit for a minimum of 40 ms
when a valid RDS group has been received. Setting the
RDS interrupt enable (RDSIEN) bit and GPO[1:0] = 01
will configure GPO to pulse low for a minimum of 5 ms
when a valid RDS group has been received. If an invalid
group is received, RDSR will not be set and GPO will
not pulse low. In standard mode RDS synchronization
(RDSS) and block error rate A, B, C and D (BLERA,
BLERB, BLERC, and BLERD) are unused and will read
0. This mode is backward compatible with earlier
firmware revisions.
Setting the RDS mode bit high places the device in RDS
verbose mode. The device sets RDSS high when
synchronized and low when synchronization is lost. If
the device is synchronized, RDS ready (RDSR) will be
set for a minimum of 40 ms when a RDS group has
been received. Setting the RDS interrupt enable
(RDSIEN) bit and GPO[1:0] = 01 will configure GPO to
pulse low for a minimum of 5 ms if the device is
synchronized and an RDS group has been received.
BLERA, BLERB, BLERC and BLERD provide
block-error levels for the RDS group. The number of bit
errors in each block within the group is encoded as
follows: 00 = no errors, 01 = one to two errors, 10 =
three to five errors, 11 = six or more errors. Six or more
errors in a block indicate the block is uncorrectable and
should not be used.
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