SI4708-C Datasheet, PDF (17/40 Pages) Silicon Laboratories – BROADCAST FM RADIO TUNER FOR PORTABLE APPLICATIONS

Si4708/09-C
4.8.2. 2-Wire Control Interface
For two-wire operation, the SCLK and SDIO pins
function in open-drain mode (pull-down only) and must
be pulled up by an external device. A transfer begins
with the START condition (falling edge of SDIO while
SCLK is high). The control word is latched internally on
rising SCLK edges and is eight bits in length, comprised
of a seven bit device address equal to 0010000b and a
read/write bit (write = 0 and read = 1).
The device acknowledges the address by driving SDIO
low after the next falling SCLK edge, for 1 cycle. For
write operations, the device acknowledge is followed by
an eight bit data word latched internally on rising edges
of SCLK. The device acknowledges each byte of data
written by driving SDIO low after the next falling SCLK
edge, for 1 cycle. An internal address counter
automatically increments to allow continuous data byte
writes, starting with the upper byte of register 02h,
followed by the lower byte of register 02h, and onward
until the lower byte of the last register is reached. The
internal address counter then automatically wraps
around to the upper byte of register 00h and proceeds
from there until continuous writes end. Data transfer
ends with the STOP condition (rising edge of SDIO
while SCLK is high). After every STOP condition, the
internal address counter is reset.
For read operations, the device acknowledge is
followed by an eight bit data word shifted out on falling
SCLK edges. An internal address counter automatically
increments to allow continuous data byte reads, starting
with the upper byte of register 0Ah, followed by the
lower byte of register 0Ah, and onward until the lower
byte of the last register is reached. The internal address
counter then automatically wraps around to the upper
byte of register 00h and proceeds from there until
continuous reads cease. After each byte of data is read,
the controller IC must drive an acknowledge (SDIO = 0)
if an additional byte of data will be requested. Data
transfer ends with the STOP condition. After every
STOP condition, the internal address counter is reset.
For details on timing specifications and diagrams, refer
to Table 6, “2-Wire Control Interface
Characteristics^1,2,3,” on page 8, Figure 4, “2-Wire
Control Interface Read and Write Timing Parameters,”
on page 9 and Figure 5, “2-Wire Control Interface Read
and Write Timing Diagram,” on page 9.
4.9. Reset, Powerup, and Powerdown
Driving the RST pin low will disable the Si4708/09 and
its control bus interface, and reset the registers to their
default settings. Driving the RST pin high will bring the
device out of reset. As the part is brought out of reset,
the SEN pin is used to select between 2-wire and 3-wire
control interface operation.
Table 8. Selecting 2-Wire or 3-Wire Control
Interface Busmode Operation
Bus Mode
SEN
3-wire
0
2-wire
1
Note: All parameters applied on rising edge of RST.
The bus mode selection method requires the use of the
SEN pin. To select 2-wire operation, the SEN pin must
be sampled high by the device on the rising edge of
RST. To select 3-wire operation, the SEN pin must be
sampled low by the device on the rising edge of RST.
When proper voltages are applied to the Si4708/09, the
ENABLE and DISABLE bits in register 02h can be used
to select between powerup and powerdown modes.
When voltage is first applied to the device, ENABLE =
DISABLE = 0. Setting ENABLE = 1 and DISABLE = 0
puts the device in powerup mode. To power down the
device, disable RDS (Si4709 only), set Reg4(5:4),
Reg4(3:2), and Reg4(1:0) to 0b10. then write 1 to the
ENABLE and DISABLE bits. After being written to 1,
both bits will get cleared as part of the internal device
powerdown sequence. To put the device back into
powerup mode, set ENABLE = 1 and DISABLE = 0 as
described above. The ENABLE bit should never be
written to a 0.
Rev. 1.2
17