SI53325 Datasheet, PDF (16/27 Pages) Silicon Laboratories – DUAL 1:5 LOW JITTER LVPECL CLOCK BUFFER

Si53325
Pin #
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
Table 12. Si53325 32-eLQFP and 32-QFN Pin Descriptions
Name
V_DD
NC
Type*
P
—
Description
Core voltage supply.
Bypass with 1.0 F capacitor and place as close to the V_DD pin as possible.
No connect. Leave this pin unconnected.
CLK0
I
Input clock 0.
CLK0
I Input clock 0 (complement).
NC
— No connect. Leave this pin unconnected.
CLK1
I
Input clock 1.
CLK1
I Input clock 1 (complement).
GND
GND Ground.
V_DD
P Core voltage supply.
Bypass with 1.0 µF capacitor and place as close to the V_DD pin as possible.
Q9
O Output clock 9 (complement).
Q9
O Output clock 9.
Q8
O Output clock 8 (complement).
Q8
O Output clock 8.
Q7
O Output clock 7 (complement).
Q7
O Output clock 7.
V_DD
P Core voltage supply.
Bypass with 1.0 µF capacitor and place as close to the V_DD pin as possible.
Q6
O Output clock 6 (complement).
Q6
O Output clock 6.
Q5
O Output clock 5 (complement).
Q5
O Output clock 5.
Q4
O Output clock 4 (complement).
Q4
O Output clock 4.
Q3
O Output clock 3 (complement).
Q3
O Output clock 3.
V_DD
P Core voltage supply.
Bypass with 1.0 µF capacitor and place as close to the V_DD pin as possible.
Q2
O Output clock 2 (complement).
16
Rev. 1.0