SI53325 Datasheet, PDF (1/27 Pages) Silicon Laboratories – DUAL 1:5 LOW JITTER LVPECL CLOCK BUFFER

Si53325
DUAL 1:5 LOW JITTER LVPECL CLOCK BUFFER
(<1.25 GHZ)
Features
 2 independant banks of LVPECL  RoHS compliant, Pb-free
outputs
 32-QFN, 32-eLQFP
 Ultra-low additive jitter: 45 fs rms typ _{ Industrial temperature range:}
 Wide frequency range: dc to
–40 to +85°C
1.25 GHz
 Footprint-compatible with
 Input compatible with LVPECL,
MC100LVEP210
LVDS, CML, HCSL, LVCMOS
 Low output-output skew: <25 ps typ
Applications
 High-speed clock distribution
 Ethernet switch/router
 Optical Transport Network (OTN)
 SONET/SDH
 PCI Express Gen 1/2/3
 Storage
 Telecom
 Industrial
 Servers
 Backplane clock distribution
Description
The Si53325 is an ultra low jitter dual 1:5 LVPECL buffer. The Si53325 utilizes
Silicon Laboratories' advanced CMOS technology to fanout clocks from dc to
1.25 GHz with guaranteed low additive jitter, low skew, and low propagation delay
variability. The Si53325 features minimal cross-talk and provides superior supply
noise rejection, simplifying low jitter clock distribution in noisy environments.
Functional Block Diagram
VDD
Power
Supply
Filtering
Ordering Information:
See page 18.
Pin Assignments
Si53325
32 31 30 29 28 27 26 25
VDD
1
24
Q3
NC
2
23
Q3
CLK0
3
CLK0
4
NC
5
CLK1
6
Exposed
GND
Pad
22
Q4
21
Q4
20
Q5
19
Q5
CLK1
7
18
Q6
GND
8
17
Q6
9 10 11 12 13 14 15 16
CLK0
CLK0
CLK1
CLK1
Q0, Q1, Q2, Q3, Q4
Q0, Q1, Q2, Q3, Q4
Q5, Q6, Q7, Q8, Q9
Q5, Q6, Q7, Q8, Q9
32 31 30 29 28 27 26 25
VDD 1
24 Q3
NC 2
23 Q3
CLK0 3
CLK0 4
NC 5
CLK1 6
Exposed
GND
Pad
22 Q4
21 Q4
20 Q5
19 Q5
CLK1 7
18 Q6
GND 8
17 Q6
9 10 11 12 13 14 15 16
Patents pending
Rev. 1.0 7/15
Copyright © 2015 by Silicon Laboratories
Si53325