SI53325 Datasheet, PDF (14/27 Pages) Silicon Laboratories – DUAL 1:5 LOW JITTER LVPECL CLOCK BUFFER

Si53325
Figure 10. Differential Total Jitter (625 MHz)
2.6. Power Supply Noise Rejection
The device supports on-chip supply voltage regulation to reject noise present on the power supply, simplifying low
jitter operation in real-world environments. This feature enables robust operation alongside FPGAs, ASICs and
SoCs and may reduce board-level filtering requirements. For more information, see “AN491: Power Supply
Rejection for Low Jitter Clocks”.
14
Rev. 1.0