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SI8285 Datasheet, PDF (15/32 Pages) Silicon Laboratories – System Safety Features
Si8285/86 Data Sheet
Electrical Specifications
Parameter
Symbol
Test Condition
Min
Typ Max Units
CBl charging current (Si8285)
IChg
CBl charging current (Si8286)
—
1
—
mA
—
0.25
—
mA
DESAT Sense to 90% VOUT Delay
tDESAT(90%)
—
220
300
ns
DESAT Sense to 10% VOUT Delay
tDESAT(10%)
0.77
2.5
2.7
µs
DESAT Sense to FLT Low Delay
tDESAT to FLT
—
220
300
ns
Reset to FLT High Delay
tRST to FLT
—
37
45
ns
Miller Clamp Parameters (Si8285 Only)
Clamp Pin Threshold Voltage
Vt Clamp
—
2.0
—
V
Miller Clamp Transistor RDS (ON)
RMC
—
1.07
—
Ω
Clamp Low Level Sinking Current
ICL
VCLMP = VSSB + 6.0
3.0
3.4
—
A
Digital Parameters
Logic High Input Threshold
VIH
2.0
—
—
V
Logic Low Input Threshold
VIL
—
—
0.8
V
Input Hysteresis
VIHYST
—
440
—
mV
High Level Output Voltage (RDY pin on-
ly)
VOH
IO = –4 mA
VDDA – 0.4 —
—
V
Low Level Output Voltage (RDY pin on-
ly)
VOL
IO = 4 mA
—
—
0.4
V
Open-Drain Low Level Output Voltage
(FLT pin only)
VDDA = 5 V,
5 kΩ pull-up resistor
—
—
200
mV
AC Switching Parameters
Propagation Delay (Low-to-High)
tPLH
CL = 200 pF
30
40
50
ns
Propagation Delay (High-to-Low)
tPHL
CL = 200 pF
30
40
50
ns
Pulse Width Distortion
PWD
|tPLH – tPHL|
—
1
5
ns
Propagation Delay Difference4
PDD
tPHLMAX – tPLHMIN
–1
—
25
ns
Rise Time
tR
CL = 200 pF
—
5.5
15
ns
Fall Time
tF
CL = 200 pF
—
8.5
20
ns
Common Mode Transient Immunity
Output = low or high (VCM =
1500 V)
35
50
— kV/µs
1. See 1. Ordering Guide for more information.
2. Minimum value of (VDD – GND) decoupling capacitor is 1 µF.
3. When performing this test, it is recommended that the DUT be soldered to avoid trace inductances, which may cause overstress
conditions.
4. Guaranteed by characterization.
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