S-8249AAP-M6T1U Datasheet, PDF (9/22 Pages) Seiko Instruments Inc – VOLTAGE MONITORING IC WITH CELL BALANCING FUNCTION

Rev.1.2_00
 Test Circuit
VOLTAGE MONITORING IC WITH CELL BALANCING FUNCTION
S-8249 Series
R_CB = 100 kΩ
R_CO = 100 kΩ
I_VDD
A
VDD
V1
VSS
S-8249
Series
CO
CB
DP
_____
CE
V2
SW1
SW2
V3
V4
SW3
SW4
V5
I_CB A I_CO A
Figure 3
Caution Unless otherwise specified in Table 8, set V2 = V3 = 0 V, and SWn (n = 1 to 4) = OFF.
_____
1. CE pin voltage "H"
_____
CE
pin
voltage
"H"
(V ) ^_____
CEH
is
defined
as
the
voltage
at
which
I_VDD
is
changed
from
I_OPE
to
I_PSV
when
V2
is
increased
from 0 V after setting V1 = V_BL − 0.1 V.
_____
2. CE pin voltage "L"
_____
CE
pin
voltage
"L"
(V ) ^_____
CEL
is
defined
as
the
voltage
at
which
I_VDD
is
changed
from
I_PSV
to
I_OPE
when
V2
is
decreased
from V_BL − 0.1 V after setting V1 = V2 = V_BL − 0.1 V.
3. DP pin voltage "H"^*1
DP pin voltage "H" (V_DPH) is defined as the voltage at which the test mode is switched when V3 is increased from
0 V after setting V1 = V_BL − 0.1 V.
4. DP pin voltage "L" ^*1
DP pin voltage "L" (V_DPL) is defined as the voltage at which the normal operation mode is switched when V3 is
decreased from V_BL − 0.1 V after setting V1 = V3 = V_BL − 0.1 V.
5. Cell balancing detection delay time
Cell balancing detection delay time (t_BU) is defined as the time from when SW1 is set to ON and V1 is set to V_BU −
0.1 V to when the CB pin output is inverted after setting V1 to V_BU + 0.1 V.
6. Cell balancing release delay time
Cell balancing release delay time (t_BL) is defined as the time from when SW1 is set to ON and V1 is set to V_BL +
0.1 V to when the CB pin output is inverted after setting V1 to V_BL − 0.1 V.
7. Overcharge detection delay time
Overcharge detection delay time (t_CU) is defined as the time from when SW1 is set to ON and V1 is set to V_CU −
0.1 V to when the CO pin output is inverted after setting V1 to V_CU + 0.1 V.
8. Overcharge release delay time
Overcharge release delay time (t_CL) is defined as the time from when SW1 is set to ON and V1 is set to V_CL +
0.1 V to when the CO pin output is inverted after setting V1 to V_CL − 0.1 V.
*1. For details about switching to the test mode by using the DP pin, refer to "5. DP pin" in " Operation".
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