S-8249AAP-M6T1U Datasheet, PDF (11/22 Pages) Seiko Instruments Inc – VOLTAGE MONITORING IC WITH CELL BALANCING FUNCTION

Rev.1.2_00
VOLTAGE MONITORING IC WITH CELL BALANCING FUNCTION
S-8249 Series
 Operation
Remark Refer to " Standard Circuit".
1. Normal status
In the S-8249 Series, if the voltage between the VDD pin and the VSS pin (V_DS) has not reached the cell
balancing detection voltage (V_BU), the CB pin output is in the high-impedance status. The CO pin output status
varies according to the output form and output logic selected, as shown in Table 10. This is the normal status.
Table 10
CO Pin Output Form and Output Logic CB Pin Output
CMOS output, active "H"
"H"
CMOS output, active "L"
"H"
Nch open-drain output, active "H"
"H"
Nch open-drain output, active "L"
"H"
CO Pin Output
"L"
"H"
"L"
"H"
2. Cell balancing status
In the S-8249 Series, if V_DS is V_BU or higher and this status continues for the cell balancing detection delay time
(t_BU) or longer, the CB pin output becomes "L". This is the cell balancing status.
The cell balancing status is released when V_DS drops to the cell balancing release voltage (V_BL) or lower and this
status continues for the cell balancing release delay time (t_BL) or longer.
The S-8249 Series includes an Nch transistor with ON resistance of 5 Ω typ. (R_CBON) between the CB pin and the
VSS pin, thus causing the cell balancing current (I_CB) to flow in cell balancing status, and the cell balancing
operation to start.
By connecting a resistor (R_CB) to the CB pin, I_CB in cell balancing status can be calculated by using the following
equation.
I_CB = V_BU / (R_CBON + R_CB)
VDD
S-8249 Series
RCB
CB
ICB
VSS
RCBON
= 5 Ω typ.
Control
circuit
Figure 5
11