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S-8243AACFT-TB-X Datasheet, PDF (9/35 Pages) Seiko Instruments Inc – BATTERY PROTECTION IC
Rev.3.1_00
BATTERY PROTECTION IC FOR 3-SERIAL OR 4-SERIAL CELL PACK
S-8243A/B Series
2. S-8243B Series
Table 7 (1 / 2)
(Ta = 25°C unless otherwise specified)
Item
Symbol
Conditions
Min.
Typ.
Max.
Unit Test circuit
DETECTION VOLTAGE
Overcharge detection voltage n
n = 1, 2, 3, 4
VCUn
3.9 V to 4.4 V, 50 mV Step
VCUn
−0.025
VCun
VCUn
+0.025
V
4
Overcharge hysteresis voltage n
n = 1, 2, 3, 4
VHCn
−0.10 V to −0.40 V, and 0 V
VHCn
−0.05
VHCn
VHCn
+0.05
V
4
Overdischarge detection voltage
n = 1, 2, 3, 4
VDLn
2.0 V to 3.0 V, 100 mV Step
VDLn
−0.08
VDLn
VDLn
+0.08
V
4
Overdischarge hysteresis voltage
n = 1, 2, 3, 4
VHDn
0.15 V to 0.70 V, and 0 V
VHDn
−0.10
VHDn
VHDn
+0.10
V
4
Overcurrent detection voltage 1
VIOV1
0.05 V to 0.3 V, 50 mV Step
VM voltage based on VDD
Overcurrent detection voltage 2 VIOV2 VM voltage based on VDD
Overcurrent detection voltage 3 VIOV3 −
VIOV1
−0.025
VIOV1
VIOV1
+0.025
V
4
0.40
0.50
0.60
V
4
VDD
×0.425
VDD
×0.5
VDD
×0.575
V
4
Temperature coefficient for
detection and release voltage*1
TCOE1 Ta = −5°C to +55°C*3
−1.0
0
1.0
mV/°C
4
Temperature coefficient for
overcurrent detection voltage*2
TCOE2 Ta = −5°C to +55°C*3
−0.5
0
0.5
mV/°C
4
0 V BATTERY CHARGING FUNCTION (The 0 V battery function is either "0 V battery charging is allowed." or "0 V battery charging is inhibited."
depending upon the product type.)
0 V battery charge starting charger
voltage
V0CHA
0 V battery charging allowed
−
0.8
1.5
V
7
0 V battery charge inhibition battery
voltage
V0INH
0 V battery charging inhibited
0.4
0.7
1.1
V
7
INTERNAL RESISTANCE
Internal resistance between
VMP and VDD
RVDM V1 = V2 = V3 = V4 = 3.5 V
500
1100
2400
kΩ
8
Internal resistance between
VMP and VSS
RVSM V1 = V2 = V3 = V4 = 1.8 V
300
700
1500
kΩ
8
VOLTAGE REGULATOR
Output voltage
VOUT VDD = 14V, IOUT = 3 mA
3.221
3.300
3.379
V
2
Line regulation
ΔVOUT1 VDD = 6 V→18 V, IOUT = 3 mA
−
5
15
mV
2
Load regulation
ΔVOUT2 VDD = 14 V, IOUT = 5 μA→3 mA
−
15
30
mV
2
BATTERY MONITOR AMP
Input offset voltage n
n = 1, 2, 3, 4
VOFFn V1 = V2 = V3 = V4 = 3.5 V
60
165
270
mV
3
Voltage gain n
n = 1, 2, 3, 4
GAMPn V1 = V2 = V3 = V4 = 3.5 V
0.2×0.99
0.2
0.2×1.01 ⎯
3
INPUT VOLTAGE, OPERATING VOLTAGE
Operating voltage between
VDD and VSS
CTL1 input voltage for High
CTL1 input voltage for Low
CTLn input voltage for High
n = 2, 3, 4
VDSOP
VCTL1H
VCTL1L
VCTLnH
−
6
−
18
V
4
−
VDD×0.8
−
−
V
6
−
−
−
VDD×0.2
V
6
−
VOUT×0.9
−
VOUT
V
3, 6
CTLn input voltage for Low
n = 2, 3, 4
VCTLnL
−
−
−
VOUT×0.1
V
3, 6
9