S-8243AACFT-TB-X Datasheet, PDF (12/35 Pages) Seiko Instruments Inc – BATTERY PROTECTION IC

BATTERY PROTECTION IC FOR 3-SERIAL OR 4-SERIAL CELL PACK
S-8243A/B Series
Rev.3.1_00
4. Overcharge detection voltages, overcharge hysteresis voltages, overdischarge detection voltages,
overdischarge hysteresis voltages, and overcurrent detection voltages (Test circuit 4)
4. 1 Overcharge detection voltages, overcharge hysteresis voltages, overdischarge detection voltages and
overdischarge hysteresis voltages
In the following V_MP = V_DD and the CDT pin is open.
The COP pin and the DOP pin should provide “Low”, which is a voltage equal to V_DD × 0.1 V or lower, in the condition
that V1 = V2 = V3 = V4 = 3.5 V.
The overcharge detection voltage V_CU1 is defined by the voltage at which COP pin voltage becomes “High”, which is
a voltage equal to V_DD × 0.9 V or higher, when the voltage V1 is gradually increased from the starting condition V1 =
3.5 V. The overcharge release voltage V_CL1 is defined by the voltage at which COP pin voltage becomes “Low” when
the voltage V1 is gradually decreased. The overcharge hysteresis voltage V_HC1 is then defined by the difference
between the overcharge detection voltage V_CU1 and the overcharge release voltage V_CL1.
The overdischarge detection voltage V_DL1 is defined by the voltage at which DOP pin voltage becomes “High” when
the voltage V1 is gradually decreased from the starting condition V1 = 3.5 V. The overdischarge release voltage
V_DU1 is defined by the voltage at which DOP pin voltage becomes “Low” when the voltage V1 is gradually increased.
The overdischarge hysteresis voltage V_HD1 is then defined by the difference between the overdischarge release
voltage V_DU1 and the overdischarge detection voltage V_DL1.
Other overcharge detection voltage V_CUn, overcharge hysteresis voltage V_HCn, overdischarge detection voltage V_DLn,
and overdischarge hysteresis voltage V_HDn ( for n = 2 to 4) are defined in the same manner as in the case for n = 1.
4. 2 Overcurrent detection voltages
Starting condition is V1 = V2 = V3 = V4 = 3.5 V, V_MP = V_DD, and the CDT pin is open. The DOP pin voltage thus
provides “Low”
The overcurrent detection voltage 1, VIOV1 is defined by the voltage difference VDD − VMP at which the DOP pin
voltage becomes “High” when the voltage of VMP pin is decreased.
Starting condition for measuring the overcurrent detection voltage 2 and 3 is V1 = V2 = V3 = V4 = 3.5 V, V_MP = V_DD
and the CDT pin voltage V_CDT = V_SS . The DOP pin voltage thus provides “Low”.
The overcurrent detection voltage 2, V_IOV2 is defined by the voltage difference V_DD−V_MP at which the DOP pin voltage
becomes “High” when the voltage of VMP pin is decreased.
The overcurrent detection delay time 2, t_IOV2 is a time needed for the DOP pin to become “High” from “Low” when the
VMP pin voltage is changed quickly to V_IOV2 min.−0.2 V from the starting condition V_MP = V_DD.
The overcurrent detection voltage 3, V_IOV3 is defined by the voltage of the VMP pin at which the DOP pin voltage
becomes “High” when the voltage of VMP pin is decreased at the speed 10 V / ms.
The overcurrent detection delay time 3, t_IOV3 is a time needed for the DOP pin to become “High” from “Low” when the
VMP pin voltage is changed quickly to V_IOV3 min.−0.2 V from the starting condition V_MP = V_DD.
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