S-8243AACFT-TB-X Datasheet, PDF (14/35 Pages) Seiko Instruments Inc – BATTERY PROTECTION IC

BATTERY PROTECTION IC FOR 3-SERIAL OR 4-SERIAL CELL PACK
S-8243A/B Series
Rev.3.1_00
8. Internal resistance (Test circuit 8)
The resistance between VDD and VMP is R_VDM and is calculated by the equation R_VDM = V_DD / I_VDM where I_VDM is a VMP
pin current after V_MP is changed to V_SS from the starting condition V1 = V2 = V3 = V4 = 3.5 V and V_MP = V_DD.
The resistance between VSS and VMP is R_VSM and is calculated by the equation R_VSM = V_DD / I_VSM where I_VSM is a VMP
pin current at the condition V1 = V2 = V3 = V4 = 1.8 V and V_MP = V_DD.
9. Pin current for CTL2 to CTL4, COP, DOP, VBATOUT (Test circuit 9)
Starting condition is V1 = V2 = V3 = V4 = 3.5 V.
Pin current for CTL2 at “High” is I_CTL2H and is obtained by setting V_CTL2 = V_OUT.
Pin current for CTL2 at “Low” is I_CTL2L and is obtained by setting V_CTL2 = V_SS.
Pin current for CTL3 and CTL4 can be obtained in the same manner as in the CTL2.
Pin current for COP at “High” is I_COH and is obtained by setting V1 = V2 = V3 = V4 = 6 V, V_MP = V_DD, and V_COP = V_DD. And
pin current for COP at “Low” is I_COL and is obtained by setting V1 = V2 = V3 = V4 = 3.5 V, V_MP = V_DD, and V_COP = 0.5 V.
Pin current for DOP at “Low” is I_DOL and is obtained by setting V1 = V2 = V3 = V4 = 3.5 V, V_MP = V_DD, and V_DOP = 0.5 V.
And pin current for COP at “High” is I_COH and is obtained by setting V1 = V2 = V3 =V4 = 3.5 V, V_MP = V_DD−1 V, and V_DOP
= V_DD−0.5 V.
Pin current for VBATOUT at “High” is I_VBATH and is obtained by setting CTL3 and CTL4 are open and V_BATOUT =
V_OFF3−0.5 V. And pin current for VBATOUT at “Low” is I_VBATL and is obtained by setting V_BATOUT = V_OFF3+0.5 V.
V1
V2
V3
V4
A
1 VDD
2 DOP
3 COP
4 VMP
5 VC1
6 VC2
7 VC3
8 VSS
VREG 16
CTL1 15
CTL2 14
CTL3 13
CTL4 12
VBATOUT 11
CCT 10
CDT 9
1 VDD
VREG 16
2 DOP
CTL1 15
3 COP
4 VMP
CTL2 14
CTL3 13
5 VC1
CTL4 12
6 VC2 VBATOUT 11
V
7 VC3
CCT 10
8 VSS
CDT 9
Test circuit 1
C1=1 μF
C1=1 μF IOUT
Test circuit 2
1 VDD
VREG 16
2 DOP
CTL1 15
3 COP
CTL2 14
V1
A
V2
A
V3
A
V4
4 VMP
5 VC1
6 VC2
7 VC3
CTL3 13
CTL4 12
VBATOUT 11
CCT 10
8 VSS
CDT 9
V
C1=1 μF
Test circuit 3
R1=1 MΩ
V1
V2
V3
V
V4
V
1 VDD
2 DOP
3 COP
4 VMP
5 VC1
6 VC2
7 VC3
8 VSS
VREG 16
CTL1 15
CTL2 14
CTL3 13
CTL4 12
VBATOUT 11
CCT 10
CDT 9
Figure 5 (1 / 2)
Test circuit 4
C1=1 μF
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