S-25C010A Datasheet, PDF (6/37 Pages) Seiko Instruments Inc – CMOS SPI SERIAL E2PROM

CMOS SPI SERIAL E²PROM
S-25C010A/020A/040A
Rev.1.0_00
„ AC Electrical Characteristics
Table 12 Measurement Conditions
Input pulse voltage
Output reference voltage
Output load
0.2 × V_CC to 0.8 × V_CC
0.5 × V_CC
100 pF
Table 13
Item
Symbol ^{VCC = 1.6 to 2.5 V}
V_CC = 2.5 to 4.5 V
V_CC = 4.5 to 5.5 V _Unit
Min.
Max.
Min.
Max.
Min.
Max.
SCK clock frequency
f_SCK
−
2.0
−
5.0
−
5.0 MHz
CS setup time during CS falling t_CSS.CL
150
−
90
−
90
−
ns
CS setup time during CS rising t_CSS.CH
150
−
90
−
90
−
ns
CS deselect time
t_CDS
200
−
90
−
90
−
ns
CS hold time during CS falling t_CSH.CL
200
−
90
−
90
−
ns
CS hold time during CS rising t_CSH.CH
150
−
90
−
90
−
ns
SCK clock time “H” ^*1
t_HIGH
200
−
90
−
90
−
ns
SCK clock time “L” ^*1
t_LOW
200
−
90
−
90
−
ns
Rising time of SCK clock ^*2
t_RSK
−
1
−
1
−
1
µs
Falling time of SCK clock ^*2
t_FSK
−
1
−
1
−
1
µs
SI data input setup time
t_DS
50
−
20
−
20
−
ns
SI data input hold time
t_DH
60
−
30
−
30
−
ns
SCK “L” hold time
during HOLD rising
t_SKH.HH
150
−
70
−
70
−
ns
SCL “L” hold time
during HOLD falling
t_SKH.HL
100
−
40
−
40
−
ns
SCK “H” setup time
during HOLD falling
t_SKS.HL
150
−
60
−
60
−
ns
SCK “H” setup time
during HOLD rising
t_SKS.HH
150
−
60
−
60
−
ns
Disable time of SO output ^*2
t_OZ
−
200
−
100
−
100
ns
Delay time of SO output
t_OD
−
150
−
70
−
70
ns
Hold time of SO output
t_OH
Rising time of SO output ^*2
t_RO
Falling time of SO output ^*2
t_FO
0
−
0
−
0
−
ns
−
100
−
40
−
40
ns
−
100
−
40
−
40
ns
Disable time of SO output
during HOLD falling ^*2
t_OZ.HL
−
200
−
100
−
100
ns
Delay time of SO output
during HOLD rising ^*2
t_OD.HH
−
150
−
50
−
50
ns
WP setup time
t_WS1
WP hold time
t_WH1
WP release / setup time
t_WS2
WP release / hold time
t_WH2
0
−
0
−
0
−
ns
0
−
0
−
0
−
ns
0
−
0
−
0
−
ns
60
−
30
−
30
−
ns
*1. The clock cycle of the SCK clock (frequency f_SCK) is 1/f_SCK µs. This clock cycle is determined by a combination of several
AC characteristics. Note that the clock cycle cannot be set as (1/f_SCK) = t_LOW (Min.) + t_HIGH (Min.) by minimizing the SCK
clock cycle time.
*2. These are values of sample and not 100% tested.
6
Seiko Instruments Inc.