S-25C010A Datasheet, PDF (11/37 Pages) Seiko Instruments Inc – CMOS SPI SERIAL E2PROM

Rev.1.0_00
CMOS SPI SERIAL E²PROM
S-25C010A/020A/040A
„ Operation
1. Status register
The status register’s organization is below. The status register can Write and Read by a specific instruction.
b7
b6
b5
b4
b3
b2
b1
b0
1
1
1
1
BP1
BP0
WEL
WIP
Block Protect Bits
Write Enable Latch
Write In Progress
Figure 10 Organization of status register
The status/control bits of the status register are as follows.
1. 1 BP1, BP0 (b3, b2) : Block Protect
Bit BP1 and BP0 are composed of the nonvolatile bit. The area size of Software Protect against WRITE instruction is
defined by them. Rewriting these bits is possible by the WRSR instruction. To protect the memory area against the
WRITE instruction, set either or both of bit BP1 and BP0 to “1”. Rewriting bit BP1 and BP0 is possible unless they are
in Hardware Protect mode ( WP pin is “L”). Refer to “„ Protect Operation” for details of “Block Protect”.
1. 2 WEL (b1) : Write Enable Latch
Bit WEL shows the status of internal Write Enable Latch. Bit WEL is set by the WREN instruction only. If bit WEL is
“1”, this is the status that Write Enable Latch is set. If bit WEL is “0”, Write Enable Latch is in reset, so that the S-
25C010A/020A/040A does not receive the WRITE or WRSR instruction. Bit WEL is reset after these operations;
• the power supply voltage is dropping
• power-on
• after performing WRDI
• after the Write operation by the WRSR instruction has completed
• after the Write operation by the WRITE instruction has completed
• after setting the WP pin to “L”
1. 3 WIP (b0) : Write In Progress
Bit WIP is Read Only and shows whether the internal memory is in the Write operation or not by the WRITE or WRSR
instruction. Bit WIP is “1” during the Write operation but “0” during any other status.
Seiko Instruments Inc.
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