S-87X_1 Datasheet, PDF (29/53 Pages) Seiko Instruments Inc – HIGH WITHSTAND-VOLTAGE VOLTAGE REGULATOR WITH RESET FUNCTION

HIGH WITHSTAND-VOLTAGE VOLTAGE REGULATOR WITH RESET FUNCTION
Rev.7.2_00
S-87x Series
4. Delay circuit
The delay circuit outputs voltage detector output (V_OR) with delay after the voltage at V_IN pin has become
release voltage (+V_DET) at the rising of VIN pin.
In Figure 22, when V_cd exceeds the reference voltage (V_ref), the output voltage pin detection voltage
output (V_OR) changes from low to high level, providing delay output. When the voltage at VIN pin falls
under the detection voltage (−V_DET), the N2 transistor turns ON, therefore the charge of the external
capacitor (C_D) is rapidly discharged and the voltage detector output (V_OR) changes from high to low level
without delay.
The external capacitor (C_D) is charged with constant current, and is practically independent of V_IN voltage.
Its delay time (t_pd) is expressed by the following equation:
t_pd (ms)=Delay coefficient (3.18 min., 5.74 typ., 8.73 max.)×C_D (nF)
I_C
V_cd
N2
+
−
VOR
V_ref
CD
C_D
Figure 22
Caution 1. Unless an output delay is needed, keep CD pin open. Do not apply external voltage
other than ground potential to CD pin, which may cause IC breakdown.
2. When designing your printed-circuit board layout, take care that no leakage current
flows to the external capacitor (C_D), otherwise the correct delay time may not be
obtained. Because the value of the constant current source (I_C) is only 195 nA, C_D to
impedance is high.
Seiko Instruments Inc.
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