S-34C02A Datasheet, PDF (27/34 Pages) Seiko Instruments Inc – 2-WIRE CMOS SERIAL E2PROM FOR DIMM SERIAL PRESENCE DETECT

2-WIRE CMOS SERIAL E2PROM FOR DIMM SERIAL PRESENCE DETECT
Rev.1.2_00
S-34C02A
6. Data hold time (t_HD.DAT = 0 ns)
If SCL and SDA of the S-34C02A are changed at the same time, it is necessary to prevent a start/stop condition from
being mistakenly recognized due to the effect of noise. If a start/stop condition is mistakenly recognized during
communication, the S-34C02A enters the standby status.
In the S-34C02A, it is recommended to set the delay time of 0.3 µs minimum from a falling edge of SCL for the SDA.
This is to prevent S-34C02A from going in a stop/start condition due to the time lag caused by the load of the bus line.
t_HD.DAT = 0.3 µs Min.
SCL
SDA
Figure 27 S-34C02A Data Hold Time
7. SDA pin and SCL pin noise suppression time
The S-34C02A includes a built-in low-pass filter at the SDA and SCL pins to suppress noise. This means that if the
power supply voltage is 5.0 V, noise with a pulse width of 160 ns or less can be suppressed.
For details of the assurable value, refer to noise suppression time (t_l) in Table 10.
300
Noise Suppression Time (t_I) Max. ₂₀₀
[ns]
100
2
3
4
5
Power Supply Voltage (V_CC)
[V]
Figure 28 Noise Suppression Time for SDA and SCL Pins
Seiko Instruments Inc.
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