S-34C02A Datasheet, PDF (20/34 Pages) Seiko Instruments Inc – 2-WIRE CMOS SERIAL E2PROM FOR DIMM SERIAL PRESENCE DETECT

2-WIRE CMOS SERIAL E²PROM FOR DIMM SERIAL PRESENCE DETECT
S-34C02A
Rev.1.2_00
8. Address Increment Timing
In the Read operation, the timing when a memory address counter is automatically incremented is at a falling edge of
the SCL clock right after the output of 8th bit.
In the Write operation, that timing is at a falling edge of the SCL clock when installing the 8th bit data.
SCL
SDA
8
9
1
R / W = 1 ACK Output D7 Output
8
9
D0 Output
Address Increment
Figure 16 Address Increment Timing in Reading
SCL
8
9
1
8
9
SDA
R/W=0
ACK Output D7 Inpit
D0 Inpit
ACK Output
Address Increment
Figure 17 Address Increment Timing in Writing
„ Write Inhibition Function at Low Power Voltage
The S-34C02A has a built-in detection circuit which operates with the low power supply voltage, cancels Write when
the power supply voltage drops and power-on. Its detection and release voltages are 1.20 V typ. (Refer to Figure 18).
The S-34C02A cancels Write by detecting a low power supply voltage when it receives a stop condition.
In the data trasmission and the Write operation, data in the address written during the low power supply voltage is not
assurable.
Power Supply Voltage
Detection Voltage (−V_DET)
1.20 V Typ.
Release Voltage (+V_DET)
1.20 V Typ.
Write Instruction cancel
Figure 18 Operation at Low Power Voltage
20
Seiko Instruments Inc.