S-34C02A Datasheet, PDF (19/34 Pages) Seiko Instruments Inc – 2-WIRE CMOS SERIAL E2PROM FOR DIMM SERIAL PRESENCE DETECT

2-WIRE CMOS SERIAL E2PROM FOR DIMM SERIAL PRESENCE DETECT
Rev.1.2_00
S-34C02A
7. 3 Sequential Read
Both in current Read and random Read, when the S-34C02A receives the 7-bit device address and Read/Write
instruction code “1” after receiving a start condition, it generates an acknowledgment signal.
When 8-bit data is output from the S-34C02A synchronizing with the SCL clock, an memory address counter in the
S-34C02A is automatically incremented at a falling edge of SCL clock right after the output of 8th bit data.
After that, the master device transmits an acknowledgment signal, the next data in the memory data address is
output. A memory address counter in the S-34C02A is incremented because the master device transmits an
acknowledge signal, so that S-34C02A keeps reading data sequentially. This is sequential read.
The Write operation ends when the master device transmits a stop condition, not an acknowledgment signal.
Although S-34C02A can read data sequentially in this sequential read, if a memory address counter reaches the
last word address, it rolls over to the first memory address.
R
E
DEVICE A
ADDRESS D
SDA
LINE
1 D7
RA
/C
WK
NO ACK from
Master Device
S
A
A
A
T
C
C
C
O
K
K
K
P
D0 D7
D0 D7
D0 D7
D0
DATA (n)
DATA (n+1)
DATA (n+2)
DATA (n+x)
ADR INC
ADR INC
Figure 15 Sequential Read
ADR INC
ADR INC
Seiko Instruments Inc.
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