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S-24C02BPPHL Datasheet, PDF (25/39 Pages) Seiko Instruments Inc – 2-WIRE CMOS SERIAL E2PROM
Rev.2.2_00
2-WIRE CMOS SERIAL E2PROM
S-24C02BPPHL
8. Data hold time (tHD.DAT = 0 ns)
If SCL and SDA of the E2PROM are changed at the same time, it is necessary to prevent the start/stop
condition from being mistakenly recognized due to the effect of noise. If a start/stop condition is mistakenly
recognized during communication, the E2PROM enters the standby status.
It is recommended that SDA is delayed from the falling edge of SCL by 0.3 µs minimum in the S-
24C02BPPHL. This is to prevent time lag caused by the load of the bus line from generating the stop (or
start) condition.
tHD.DAT = 0.3 µs Min.
SCL
SDA
Figure 26 E2PROM Data Hold Time
9. SDA pin and SCL pin noise suppression time
The S-24C02BPPHL includes a built-in low-pass filter to suppress noise at the SDA and SCL pins. This
means that if the power supply voltage is 5.0 V (at room temperature), noise with a pulse width of 150 ns or
less can be suppressed.
The guaranteed for details, refer to noise suppression time (tI) in Table 9.
300
Noise suppression time (tI) Max.
200
[ns]
100
2345
Power supply voltage (VCC)
[V]
Figure 27 Noise Suppression Time for SDA and SCL Pins
Seiko Instruments Inc.
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