S-24C02BPPHL Datasheet, PDF (18/39 Pages) Seiko Instruments Inc – 2-WIRE CMOS SERIAL E2PROM

2-WIRE CMOS SERIAL E²PROM
S-24C02BPPHL
Rev.2.2_00
8. Address increment timing
The address increment timing is as follows. During a read operation, the memory address counter is
automatically incremented at the falling edge of the SCL clock (where the 8th bit of read data is output).
During a write operation, the memory address counter is also automatically incremented at the falling edge of
the SCL clock when the 8th bit of write data is fetched.
SCL
8
9
1
8
9
SDA
R / W = 1 ACK output
D7 output
D0 output
Address increment
Figure 16 Address Increment Timing in Read Operation
SCL
8
9
1
8
9
SDA
R/W=0
ACK output D7 input
D0 input
ACK output
Address increment
Figure 17 Address Increment Timing in Write Operation
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Seiko Instruments Inc.