S-24CS16A Datasheet, PDF (20/53 Pages) Seiko Instruments Inc – 2-WIRE CMOS SERIAL E2PROM

2-WIRE CMOS SERIAL E²PROM
S-24CS16A
Rev.4.3_00
8. Address Increment Timing
The timing for the automatic address increment is the falling edge of the SCL clock for the 8th bit of the read data in
read operation and the falling edge of the SCL clock for the 8th bit of the received data in write operation.
SCL
SDA
8
9
1
R / W = 1 ACK Output D7 Output
8
9
D0 Output
Address Increment
Figure 21 Address Increment Timing in Reading
SCL
8
9
1
8
9
SDA
R/W=0
ACK Output D7 Inpit
D0 Inpit
ACK Output
Address Increment
Figure 22 Address Increment Timing in Writing
„ Write Inhibition Function at Low Power Voltage
The S-24CS16A has a detection circuit for low power voltage. The detection circuit cancels a write instruction when the
power voltage is low or the power switch is on. The detection voltage is 1.85 V typically and the release voltage is 1.95
V typically, the hysteresis of approximate 0.1 V thus exists. (See Figure 23.)
When a low power voltage is detected, a write instruction is canceled at the reception of a stop condition.
When the power voltage lowers during a data transmission or a write operation, the data at the address of the operation
is not assured.
Power supply voltage
Detection voltage (−V_DET)
1.85 V Typ.
Hysteresis width
0.1 V approximately
Release voltage (+V_DET)
1.95 V Typ.
Write Instruction cancel
Figure 23 Operation at Low Power Voltage
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Seiko Instruments Inc.