S-35740C01A-K8T2U Datasheet, PDF (19/31 Pages) Seiko Instruments Inc – Operation temperature range

FOR AUTOMOTIVE 125°C OPERATION 2-WIRE INTERVAL TIMER CONVENIENCE TIMER
Rev.1.1_00
S-35740 Series
7. Read operation of fixed-cycle interrupt signal setting register
Perform the read operation of fixed-cycle interrupt signal setting register with the restart format. Regarding the restart
format, refer to "4. Data transmission format".
When performing the read operation of fixed-cycle interrupt signal setting register, set the ENBL pin to "H". If the
ENBL pin is set to "L", the time register data is read.
Transmit the start condition and the slave address from the master device. The slave address of the S-35740 Series
is specified to "0110010". Next, transmit "0" to the read / write bit.
B7 in the 2nd byte is an address pointer. Set B7 to "0" when reading the fixed-cycle interrupt signal setting register.
Next, transmit the dummy data to B6 to B1. Make sure to set B0 to "1" since it is a test bit. This processing is called
"dummy write".
Then transmit the start condition, the slave address and the read / write bit. The data of the fixed-cycle interrupt
setting register can be read when the read / write bit is set to "1".
Consequently, the fixed-cycle interrupt signal setting register is output from the S-35740 Series. Each byte from B7 is
transmitted.
When the read operation of the fixed-cycle interrupt signal setting register is finished, transmit "1" (NO_ACK) to the
acknowledge after B0 output from the master device, and then transmit the stop condition.
The fixed-cycle interrupt signal setting register is a 2-byte register. "1" is read if the read operation is performed
continuously after reading 2 bytes of the fixed-cycle interrupt signal setting register.
Regarding the fixed-cycle interrput signal setting register, refer to " Configuration of Registers".
Moreover, the internal address pointer is reset if recognizing the stop condition. Therefore, do not transmit the stop
condition after dummy write operation. The time register is read if performing the read operation of the register after
transmitting the stop condition.
1
9
18
1
9
18
27
SCL
SDA
01100100 0
1
01100101
B7
B1R/W B7
B0
B7
B1R/W B7
B0 B7
B0 B7
Slave address
(0110010)
Dummy data^*1
Slave address Fixed-cycle interrupt signal setting register
(0110010)




























(2byte)
Make sure to set B0 to "1" since it is a test bit.
Set B7 as an address pointer
Input NO_ACK after
the 2nd byte transmission
Dummy write
: _{Master device input data}
: _{S-35740 output data}
*1. Set "0" or "1" since they are dummy data.
Figure 25 Read Timing of Fixed-cycle Interrpt Signal Setting Register
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