S-35740C01A-K8T2U Datasheet, PDF (18/31 Pages) Seiko Instruments Inc – Operation temperature range

FOR AUTOMOTIVE 125°C OPERATION 2-WIRE INTERVAL TIMER CONVENIENCE TIMER
S-35740 Series
Rev.1.1_00
5. Read operation of time register
Transmit the start condition and slave address from the master device. The slave address of the S-35740 Series is
specified to "0110010". The data of the time register can be read when the read / write bit is "1".
The 2nd byte to the 4th byte are used as the time register. Each byte from B7 is transmitted.
When the read operation of the time register is finished, transmit "1" (NO_ACK) to the acknowledge after B0 is output
from the master device, and then transmit the stop condition.
The time register is a 3-byte register. "1" is read if the read operation is performed continuously after reading 3 bytes
of the time register. Regarding the time register, refer to " Configuration of Registers".
1
9
SCL
18
27
36
SDA
01100101
B7
B1 R/W B7
B0 B7
B0 B7
B0
Slave address
(0110010)
Time register (3-byte)
Take in the counter value at this timing and transmit it as a serial data.
: Master device input data
: S-35740 output data
Input NO_ACK after the 3rd byte data is transmitted.
Figure 23 Read Timing of Time Register
6. Write operation of fixed-cycle interrupt signal setting register
Transmit the start condition and slave address from the master device. The slave address of the S-35740 Series is
specified to "0110010". Next, transmit "0" to the the read / write bit.
Transmit dummy data to the 2nd byte. However, make sure to set B0 to "1" since it is a test bit.
B7 to B0 in the 3rd byte and B7 to B5 in the 4th byte are used as the fixed-cycle interrupt signal setting register.
Set B6 to B1 in the 2nd byte and B4 to B3 in the 4th byte to "0" or "1" since they are dummy data.
B2 to B0 (RST2 to RST0) in the 4th byte are used as a register to input the timer reset command. The timer is reset
when transmitting RST2 = "0", RST1 = "1" and RST0 = "0". When not resetting the timer, transmit the data except for
the above mentioned ones, such as RST2 = "1", RST1 = "1" and RST0 = "1" to the fixed-cycle interrupt signal setting
register.
Transmit the stop condition from the master device to finish the access operation.
Regarding the fixed-cycle interrupt signal setting register, refer to " Configuration of Registers".
Write operation of the fixed-cycle interrupt signal setting register is performed each byte, so transmit the data in
2-byte unit. Note that the S-35740 Series may not operate as desired if the data is not transmitted in 2-byte unit.
1
9
18
27
36
SCL
1 Hz to
128 Hz 256 Hz to
1 kHz, RST[2:0]
Write timing
Write timing
SDA
0 1 1 00 1 00 1
1
B7
B1 R/W B7
B0 B7
B0 B7
B0
Slave address
(0110010)
Dummy data^{*1 Fixed-cycle interrupt signal setting register
(2byte)}
Make sure to set B0 to "1" since it is a test bit.
Set B7 as an address pointer
: _{Master device input data}
: _{S-35740 output data}
*1. Set "0" or "1" since they are dummy data.
Figure 24 Write Timing of Fixed-cycle Interrupt Signal Setting Register
18