S-8233B Datasheet, PDF (18/26 Pages) Seiko Instruments Inc – BATTERY PROTECTION IC (FOR A 3-SERIAL-CELL PACK)

BATTERY PROTECTION IC FOR 3-SERIAL-CELL PACK
S-8233B Series
Rev.4.2_00
„ Battery Protection IC Connection Example
Battery 1
R11
C1
R1
R12
Battery 2
C2
R2
R13
Battery 3
C3
R3
FET-A
FET1
DOP
VCC
CD1
FET-B
COP
Nch open
drain
R6
1 MΩ
R5
10 KΩ
VMP
CTL
EB+
CTL logic is “normal” (S-8233BA)
VSS(GND): Normal operation
Floating or VCC: Inhibit charging
and discharging.
CTL logic is “reverse” (S-8233BB)
Floating or VCC: Normal operation
VSS(GND): Inhibit charging and
discharging.
R7
1 KΩ
FET2
VC1
CD2
FET3
VC2
CD3
VSS
S-8233B series
CCT
C4
Over charge delay
time setting
CDT
C5
Over discharge delay
time setting
FET-C
High: Inhibit over
discharge detection.
COVT
C6
Over current delay
time setting
EB -
Figure 9
[Description of Figure 9]
z R11, R12, and R13 are used to adjust the battery conditioning current. The conditioning current during
over charge detection is given by Vcu (over charge detection voltage)/R (R: resistance). To disable the
conditioning function, open CD1, CD2, and CD3.
z The over charge detection delay time (t_CU1 to t_CU3), over discharge detection delay time (t_DD1 to t_DD3), and
over current detection delay time (t_I0V1) are changed with external capacitors (C4 to C6). See the
electrical characteristics.
z R6 is a pull-up resistor that turns FET-B off when the COP terminal is opened. Connect a 100 kΩ to 1
MΩ resistor.
z R5 is used to protect the IC if the charger is connected in reverse. Connect a 10 kΩ to 50 kΩ resistor.
z If capacitor C6 is absent, rush current occurs when a capacitive load is connected and the IC enters the
over current mode. C6 must be connected to prevent it.
z If capacitor C5 is not connected, the IC may enter the over discharge condition due to variations of
battery voltage when the over current occurs. In this case, a charger must be connected to return to the
normal condition. To prevent this, connect an at least 0.01 μF capacitor to C5.
z If a leak current flows between the delay capacitor connection terminal (CCT, CDT, or COVT) and VSS,
the delay time increases and an error occurs. The leak current must be 100 nA or less.
z Over discharge detection can be disabled by using FET-C. The FET-C off leak must be 0.1 μA or less.
If over discharge is inhibited by using this FET, the current consumption does not fall below 0.1 μA even
when the battery voltage drops and the IC enters the over discharge detection mode.
z R1, R2, and R3 must be 1 kΩ or less.
z R7 is the protection of the CTL when the CTL terminal voltage higher than V_CC voltage. Connect a 300 Ω
to 5 kΩ resistor. If the CTL terminal voltage never greater than the V_CC voltage (ex. R7 connect to V_SS),
without R7 resistance is allowed .
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Seiko Instruments Inc.