S-8233B Datasheet, PDF (14/26 Pages) Seiko Instruments Inc – BATTERY PROTECTION IC (FOR A 3-SERIAL-CELL PACK)

BATTERY PROTECTION IC FOR 3-SERIAL-CELL PACK
S-8233B Series
Rev.4.2_00
Over discharge condition
If any one of the battery voltages falls below the over discharge detection voltage (V_DD) during discharging
under normal condition and it continues for the over discharge detection delay time (t_DD) or longer, the
discharging FET turns off and discharging stops. This condition is called the over discharge condition.
When the discharging FET turns off, the VMP terminal voltage becomes equal to the V_SS voltage and the
IC's current consumption falls below the power-down current consumption (I_PDN). This condition is called
the power-down condition. The VMP and VSS terminals are shorted by the R_VSM resistor under the over
discharge and power-down conditions.
The power-down condition is canceled when the charger is connected and the voltage between VMP and
V_SS is 3.0 V or higher (over current detection voltage 3). When all the battery voltages becomes equal to
or higher than the over discharge release voltage (V_DU) in this condition, the over discharge condition
changes to the normal condition.
Delay circuits
The over charge detection delay time (t_CU1 to t_CU3), over discharge detection delay time (t_DD1 to t_DD3), and
over current detection delay time 1 (t_I0V1) are changed with external capacitors (C4 to C6).
The delay times are calculated by the following equations:
Min. Typ. Max.
t_CU[S] =Delay factor ( 1.07, 2.13, 3.19)×C4 [uF]
t_DD[S] =Delay factor ( 0.20, 0.40, 0.60)×C5 [uF]
t_IOV1[S]=Delay factor ( 0.10, 0.20, 0.30)×C6 [uF]
Caution: The delay time for over current detection 2 and 3 is fixed by an internal IC circuit. The
delay time cannot be changed via an external capacitor.
CTL terminal
[If the CTL logic is “normal”]<S-8233BA, S-8233BC, S-8233BE>
If the CTL terminal is floated under normal condition, it is pulled up to the V_CC potential in the IC, and both
the charging and discharging FETs turn off to inhibit charging and discharging. Both charging and
discharging are also inhibited by applying the VCC terminal to the CTL terminal externally. At this time,
the VMP and VCC terminals are shorted by the R_VCM resistor.
When the CTL terminal becomes equal to V_SS potential, charging and discharging are enabled and go
back to their appropriate conditions for the battery voltages.
[If the CTL logic is“reverse”]<S-8233BB, S-8233BD>
When the CTL terminal becomes equal to V_SS potential, both the charging and discharging FETs turn off
to inhibit charging and discharging. If the CTL terminal is floated under normal condition, charging and
discharging are enabled and go back to their appropriate conditions for the battery voltages.
Caution Please note unexpected behavior might occur when electrical potential difference
between the CTL pin ('L' level) and VSS is generated through the external filter
(R_VSS and C_VSS) as a result of input voltage fluctuations.
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Seiko Instruments Inc.