S-13D1 Datasheet, PDF (18/45 Pages) Seiko Instruments Inc – SUPER-SMALL PACKAGE 2-CIRCUIT BUILT-IN DELAY FUNCTION HIGH RIPPLE-REJECTION LOW DROPOUT CMOS VOLTAGE REGULATOR

SUPER-SMALL PACKAGE 2-CIRCUIT BUILT-IN DELAY FUNCTION HIGH RIPPLE-REJECTION LOW DROPOUT CMOS VOLTAGE REGULATOR
S-13D1 Series
Rev.1.3_01
 Operation
1. Basic operation
Figure 23 shows the block diagram of the S-13D1 Series.
The error amplifier compares the reference voltage (Vref) with feedback voltage (Vfb), which is the output voltage
resistance-divided by feedback resistors (Rs and Rf). It supplies the gate voltage necessary to maintain the constant
output voltage which is not influenced by the input voltage and temperature change, to the output transistor.
VIN
Current
supply
V_ref
Error
amplifier
−
+
*1
R_f
VOUT
Reference voltage
circuit
V_fb
R_s
VSS
*1. Parasitic diode
Figure 23
2. Output transistor
In the S-13D1 Series, a low on-resistance P-channel MOS FET is used as the output transistor.
Be sure that VOUT does not exceed VIN + 0.3 V to prevent the voltage regulator from being damaged due to reverse
current flowing from the VOUT pin through a parasitic diode to the VIN pin, when the potential of VOUT became higher
than VIN.
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