S-8264AAA-I8T1U Datasheet, PDF (17/36 Pages) Seiko Instruments Inc – BATTERY PROTECTION IC FOR 2-SERIAL

Rev.4.2_02
BATTERY PROTECTION IC FOR 2-SERIAL TO 4-SERIAL-CELL PACK (SECONDARY PROTECTION)
S-8264A/B/C Series
4. Test Mode
In the S-8264A/B/C Series, the overcharge detection delay time (t_CU) can be shortened by entering the test mode.
The test mode can be set by retaining the VDD pin voltage 8.5 V or more higher than the SENSE pin voltage for at least
80 ms (V1 = V2 = V3 = V4 = 3.5 V, Ta = 25°C). The status is retained by the internal latch and the test mode is retained
even if the VDD pin voltage is decreased to the same voltage as that of the SENSE pin.
When CO becomes “H” when the delay time has elapsed after overcharge detection, the latch for retaining the test
mode is reset and the S-8264A/B Series exits from the test mode.
VDD pin voltage SENSE pin voltage
Pin voltage
8.5 V or
more
V_CUn
Battery voltage
(n = 1 to 4)
V_HCn
Test mode
t_TST = 80 ms max.
CO pin
*1
t_CL
*1. In the product tCU = 4 s Typ. during normal mode, tCU = 64 ms Typ.
In the product tCU = 2 s Typ. during normal mode, tCU = 32 ms Typ.
In the product tCU = 5.65 s Typ. during normal mode, tCU = 88 ms Typ.
Figure 9
Caution
1. When the VDD pin voltage is decreased to lower than the UVLO voltage of 2 V (Typ.), the
S-8264A/B/C Series returns to the normal mode.
2. Set the test mode when no batteries are overcharged.
3. The overcharge release delay time (t_CL) is not shortened in the test mode.
4. The overcharge timer reset delay time (t_TR) is not shortened in the test mode.
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