S-8232 Datasheet, PDF (13/27 Pages) Seiko Instruments Inc – BATTERY PROTECTION IC FOR 2-SERIAL-CELL PACK

Rev.5.4_00
BATTERY PROTECTION IC FOR 2-SERIAL-CELL PACK
S-8232 Series
„ Operation
Normal Condition ^{*1, *2}
This IC monitors the voltages of the two serially connected batteries and the discharge current to control
charging and discharging. When the voltages of two batteries are in the range from the overdischarge
detection voltage (V_{DD1, 2}) to the overcharge detection voltage (V_{CU1, 2}), and the current flowing through the
batteries becomes equal or lower than a specified value (the VM pin voltage is equal or lower than
overcurrent detection voltage 1), the charging and discharging FETs are turned on. In this condition,
charging and discharging can be carried out freely. This condition is called normal condition. In this
condition, the VM and VSS pins are shorted by the RVSM resistor.
Overcurrent Condition
When the discharging current becomes equal to or higher than a specified value (the VM pin voltage is
equal to or higher than the overcurrent detection voltage) during discharging under normal condition and
it continues for the overcurrent detection delay time (t_IOV) or longer, the discharging FET is turned off to
stop discharging. This condition is called overcurrent condition. The VM and VSS pins are shorted by
the RVSM resistor at this time. The charging FET is also turned off. When the discharging FET is off and
a load is connected, the VM pin voltage equals the V_CC potential.
The overcurrent condition returns to the normal condition when the load is released and the impedance
between the EB− and EB+ pins (refer to the Figure 8) is 200 MΩ or higher. When the load is released,
the VM pin, which is shorted to the VSS pin with the RVSM resistor, goes back to the V_SS potential. The
IC detects that the VM pin potential returns to overcurrent detection voltage 1 (V_IOV1) or lower and returns
to the normal condition.
Overcharge Condition
Following two cases are detected as overcharge conditions :
(1) If one of the battery voltages becomes higher than the overcharge detection voltage (V_{CU1, 2})
during charging under normal condition and it continues for the overcharge detection delay time
(t_{CU1, 2}) or longer, the charging FET turns off to stop charging.
(2) If one of the battery voltages becomes higher than the auxiliary overcharge detection voltage
(V_{CUaux1, 2}) the charging FET turns off immediately to stop charging. The VM and VSS pins are
shorted by the RVSM resistor under the overcharge condition.
The auxiliary overcharge detection voltages (V_{CUaux1, 2}) are correlated with the overcharge detection
voltages (V_{CU1, 2}) and are defined by following equations :
V_{CUaux1, 2} [V] = 1.25 × V_{CU1, 2} [V]
or for no overcharge hysteresis type (V_{CU1, 2} = V_{CD1, 2}) V_{CUaux1, 2} [V] = 1.11 × V_{CU1, 2} [V]
The overcharge condition is released in two cases :
(1) The battery voltage which exceeded the overcharge detection voltage (V_{CU1, 2}) falls below the
overcharge release voltage (V_{CD1, 2}), the charging FET turns on and the normal condition returns.
(2) If the battery voltage which exceeded the overcharge detection voltage (V_{CU1, 2}) is equal or higher
than the overcharge release voltage (V_{CD1, 2}), but the charger is removed, a load is placed, and
discharging starts, the charging FET turns on and the normal condition returns.
The release mechanism is as follows : the discharge current flows through an internal parasitic diode of
the charging FET immediately after a load is installed and discharging starts, and the VM pin voltage
increases by about 0.6 V from the VSS pin voltage momentarily. The IC detects this voltage (overcurrent
detection voltage 1 or higher), releases the overcharge condition and returns to the normal condition.
Overdischarge Condition
If any one of the battery voltages falls below the overdischarge detection voltage (V_{DD1, 2}) during
discharging under normal condition and it continues for the overdischarge detection delay time (t_{DD1, 2}) or
longer, the discharging FET turns off and discharging stops. This condition is called the overdischarge
condition. When the discharging FET turns off, the VM pin voltage becomes equal to the V_CC voltage and
the IC’s current consumption falls below the power-down current consumption (I_PDN). This condition is
called the power-down condition. The VM and VCC pins are shorted by the RVCM resistor under the
overdischarge and power-down conditions.
The power-down condition is canceled when the charger is connected and the voltage between VM and
VCC is overcurrent detection voltage 2 or higher. When all the battery voltages becomes equal to or
higher than the overdischarge release voltage (V_{DU1, 2}) in this condition, the overdischarge condition
changes to the normal condition.
Seiko Instruments Inc.
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