S-5725CNBL9-M3T1U Datasheet, PDF (13/31 Pages) Seiko Instruments Inc – HIGH-SPEED BIPOLAR HALL EFFECT LATCH

Rev.2.5_01
HIGH-SPEED BIPOLAR HALL EFFECT LATCH
S-5725 Series
2. 3 S-5725JxBxx
Item
Power supply voltage
Current consumption
Current consumption during
power-down
Output voltage
Leakage current
Awake mode time
Sleep mode time
Operating cycle
Enabling pin input voltage "L"
Enabling pin input voltage "H"
Enabling pin input current "L"
Enabling pin input current "H"
Power-down transition time
Enable transition time
Output logic update time after
inputting "H" to enabling pin
Table 14
Symbol
VDD
IDD
Average value
(Ta = +25°C, VDD = 5.0 V, VSS = 0 V unless otherwise specified)
Condition
Min.
Typ.
Max.
Unit
Test
Circuit
−
2.7
5.0 5.5
V
−
− 1400.0 2000.0 μA 1
IDD2
VCE = VSS
−
−
1 μA 6
Nch open-drain Output transistor Nch,
output product
IOUT = 2 mA
−
−
VOUT
CMOS output
Output transistor Nch,
IOUT = 2 mA
−
−
product
Output transistor Pch, VDD −
IOUT = −2 mA
0.4
−
ILEAK
Nch open-drain output product
Output transistor Nch, VOUT = 5.5 V
−
−
0.4 V
2
0.4 V
2
−
V
3
1 μA 4
tAW
−
−
50
−
μs
−
tSL
−
−
0
−
μs
−
tCYCLE tAW + tSL
VCEL
−
VCEH
ICEL
−
VDD = 5.0 V, VCE = 0 V
−
50 100 μs
−
−
−
VDD ×
0.3
V
−
VDD ×
0.7
−
−
V
−
−1
−
1 μA 7
ICEH
VDD = 5.0 V, VCE = 5.0 V
−1
−
1 μA 8
tOFF
−
−
−
100 μs
−
tON
−
−
−
100 μs
−
tOE
−
−
−
200 μs
−
13