S-5725CNBL9-M3T1U Datasheet, PDF (12/31 Pages) Seiko Instruments Inc – HIGH-SPEED BIPOLAR HALL EFFECT LATCH

HIGH-SPEED BIPOLAR HALL EFFECT LATCH
S-5725 Series
Rev.2.5_01
2. 2 S-5725IxBxx
Table 13
Item
Power supply voltage
Current consumption
Current consumption during
power-down
Output voltage
Leakage current
Awake mode time
Symbol
VDD
IDD
Average value
(Ta = +25°C, VDD = 5.0 V, VSS = 0 V unless otherwise specified)
Condition
Min.
Typ.
Max.
Unit
Test
Circuit
−
2.7 5.0 5.5
V
−
− 60.0 90.0 μA
1
IDD2
VCE = VSS
−
−
1
μA
6
Nch open-drain
output product
Output transistor Nch,
IOUT = 2 mA
−
−
0.4
V
2
VOUT
CMOS output
Output transistor Nch,
IOUT = 2 mA
−
−
0.4
V
2
product
Output transistor Pch, VDD −
IOUT = −2 mA
0.4
−
−
V
3
ILEAK
Nch open-drain output product
Output transistor Nch, VOUT = 5.5 V
−
−
1
μA
4
tAW
−
− 0.05 −
ms
−
Sleep mode time
tSL
−
− 1.20 −
ms
−
Operating cycle
tCYCLE
tAW + tSL
Enabling pin input voltage "L" VCEL
−
Enabling pin input voltage "H" VCEH
Enabling pin input current "L" ICEL
−
VDD = 5.0 V, VCE = 0 V
− 1.25 2.50 ms
−
−
−
VDD ×
0.3
V
−
VDD ×
0.7
−
−
V
−
−1
−
1
μA
7
Enabling pin input current "H" ICEH
VDD = 5.0 V, VCE = 5.0 V
−1
−
1
μA
8
Power-down transition time tOFF
−
−
− 100 μs
−
Enable transition time
tON
Output logic update time after
inputting "H" to enabling pin
tOE
−
−
− 100 μs
−
−
−
− 200 μs
−
12