S-13A1 Datasheet, PDF (13/74 Pages) Seiko Instruments Inc – HIGH RIPPLE-REJECTION LOW DROPOUT HIGH OUTPUT CURRENT CMOS VOLTAGE REGULATOR

HIGH RIPPLE-REJECTION LOW DROPOUT HIGH OUTPUT CURRENT CMOS VOLTAGE REGULATOR
Rev.2.1_00
S-13A1 Series
2. HSOP-6
Top view
654
123
Figure 10
Table 9 Types in Which Output Voltage is Internally Set
Pin No.
Symbol
Description
1
VOUT
Output voltage pin
2
VSS
GND pin
3
ON / OFF ON / OFF pin
4
SSC^*1
Inrush current limit pin
5
VSS
GND pin
6
VIN
Input voltage pin
*1. Connect a capacitor between the SSC pin and the VSS pin.
The inrush current limit time of the VOUT pin at power-on or at
the time when the ON / OFF pin is set to ON can be adjusted
according to the capacitance.
Moreover, the SSC pin is available even when it is open.
For details, refer to " Selection of Capacitor for Inrush
Current Limit (C_SS) (Types in Which Output Voltage is
Internally Set of HSOP-8A, HSOP-6, SOT-89-5)".
Table 10 Types in Which Output Voltage is Externally Set
Pin No.
Symbol
Description
1
VOUT
Output voltage pin
2
VSS
GND pin
3
VADJ
Output voltage adjustment pin
4
ON / OFF ON / OFF pin
5
VSS
GND pin
6
VIN
Input voltage pin
13