S-13A1 Datasheet, PDF (12/74 Pages) Seiko Instruments Inc – HIGH RIPPLE-REJECTION LOW DROPOUT HIGH OUTPUT CURRENT CMOS VOLTAGE REGULATOR

HIGH RIPPLE-REJECTION LOW DROPOUT HIGH OUTPUT CURRENT CMOS VOLTAGE REGULATOR
S-13A1 Series
Rev.2.1_00
 Pin Configurations
1. HSOP-8A
Top view
1
8
2
7
3
6
4
5
Bottom view
8
1
7
2
6
3
5
4
*1
*1. Connect the heat sink of backside at
shadowed area to the board, and set
electric potential GND.
However, do not use it as the function
of electrode.
Figure 9
Table 7 Types in Which Output Voltage is Internally Set
Pin No.
Symbol
Description
1
VOUT
Output voltage pin
2
ON / OFF
ON / OFF pin
3
NC^*1
No connection
4
VSS
GND pin
5
SSC^*2
Inrush current limit pin
6
NC^*1
No connection
7
NC^*1
No connection
8
VIN
Input voltage pin
*1. The NC pin is electrically open.
The NC pin can be connected to the VIN pin or the VSS pin.
*2. Connect a capacitor between the SSC pin and the VSS pin.
The inrush current limit time of the VOUT pin at power-on or at
the time when the ON / OFF pin is set to ON can be adjusted
according to the capacitance.
Moreover, the SSC pin is available even when it is open.
For details, refer to " Selection of Capacitor for Inrush
Current Limit (C_SS) (Types in Which Output Voltage is
Internally Set of HSOP-8A, HSOP-6, SOT-89-5)".
Table 8 Types in Which Output Voltage is Externally Set
Pin No.
Symbol
Description
1
VOUT
Output voltage pin
2
VADJ
Output voltage adjustment pin
3
NC^*1
No connection
4
VSS
GND pin
5
ON / OFF
ON / OFF pin
6
NC^*1
No connection
7
NC^*1
No connection
8
VIN
Input voltage pin
*1. The NC pin is electrically open.
The NC pin can be connected to the VIN pin or the VSS pin.
12